STA methodology engineer

NXP Semiconductors; Bengaluru; On-site; INR 2,500,000 - 4,500,000; Full time

Job summary

NXP Semiconductors in Bengaluru seeks an experienced STA Methodology Engineer to benchmark logic libraries across multiple technology nodes using synthesis and PNR-based flows on real chips. You will partner with Timing Methodology and Signoff teams to define robust STA strategies.

The role requires 10–12 years in STA, strong knowledge of timing constraints, DRCs, and multi-voltage flows, plus Python scripting for automation and robust collaboration across global teams.

Qualifications

• Bachelor’s or Master’s degree in Electrical or Electronics Engineering required.
• 10–12 years hands-on STA experience with tape-out as block owner or lead.
• Deep understanding of STA concepts, timing constraints, and closure at block/SoC levels.
• Proficient in addressing DRCs, annotation, multivoltage flows, noise and crosstalk.

Responsibilities

• Benchmark logic libraries across advanced technology nodes using synthesis and PNR flows.
• Collaborate with Timing Methodology and Signoff teams to refine timing constraints.
• Develop and maintain benchmarking frameworks for constraint validation and STA methodology evaluation.
• Perform comprehensive STA including timing analysis, DRCs, annotation issues, multivoltage flow enablement, noise and crosstalk.
• Contribute to automation of STA flows and methodologies.

Skills

STA knowledge

Timing analysis

Cross-functional collaboration

Python scripting

Education

Bachelor’s or Master’s degree in Electrical or Electronics Engineering

Tools

EDA tools

Job description

Job Title

STA Methodology Engineer

Team

CTO-DE-FDIP-Logic Libraries

Location

Bengaluru

Experience Level

10–12 Years

Employment Type

Full-Time

Role Overview

We are seeking a highly skilled and experienced STA Methodology Engineer to join our CTO-DE-FDIP-Logic Libraries team. In this role, you will be responsible for benchmarking various logic libraries across multiple technology nodes (40nm, 14nm, 10nm, 7nm, 5nm) using synthesis and PNR-based flows on real-world chips and blocks. You will collaborate closely with Timing Methodology and Signoff teams to ensure robust and efficient STA methodologies.

Key Responsibilities

• Benchmark logic libraries across advanced technology nodes using synthesis and PNR flows.
• Collaborate with cross-functional teams to validate and refine timing constraints.
• Develop and maintain benchmarking frameworks for constraint validation and STA methodology evaluation.
• Perform comprehensive STA including timing analysis, DRCs, annotation issues, multivoltage flow enablement, noise and crosstalk analysis using Logic Libraries Integration flow checks.
• Contribute to the development and automation of STA flows and methodologies.

Required Qualifications

• Bachelor’s or Master’s degree in Electrical or Electronics Engineering.
• 10–12 years of hands-on experience in STA, with proven tape-out experience as a block owner or lead.
• Deep understanding of STA concepts, timing constraints, and closure methodologies at both block and SoC levels.
• Proficient in handling timing-related issues such as DRCs, annotation, multivoltage flows, noise, and crosstalk.
• Strong collaboration skills and ability to work across teams to drive methodology improvements.

Preferred Skills

• Proficiency in Python scripting.
• Overview/understanding of AI/GenAI would be added advantage.
• Experience in developing or enhancing STA flow automation.
• Familiarity with industry-standard EDA tools and flows.

Soft Skills

• Self-motivated with a proactive approach to problem-solving.
• Strong communication and interpersonal skills.
• Ability to work independently and as part of a global team.

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