Senior DFT Engineer

ACL Digital; Bengaluru; Vor Ort; INR 3.000.000 - 6.000.000; Vollzeit

Zusammenfassung

ACL Digital invites applications for a Senior DFT Engineer role in Bangalore, with 6+ years of hands-on experience in core DFT methods. The candidate will lead DFT flow across complex SoC designs, including Scan Insertion, ATPG, MBIST, and boundary scan.

Collaboration with PD/Synthesis/STA teams is essential for timing closure and coverage. The role requires strong experience with industry tools (Tessent, DFTMAX, TetraMAX, Modus) and silicon debugging, with immediate to 15 days notice optional.

Qualifikationen

• 6+ years of hands-on experience in core DFT methodology and implementation.
• Experience leading end-to-end DFT flow for complex designs.
• Strong knowledge of DFT principles and silicon debugging.

Aufgaben

• Lead and execute end-to-end DFT flow across complex SoC/ASIC designs.
• Implement Scan Insertion, ATPG, MBIST, and Boundary Scan (IJTAG / IEEE 1149.1 / 1500 / 1687).
• Conduct gate-level simulations with SDF back-annotation and resolve timing/simulation issues.
• Collaborate with physical design, synthesis, and STA teams to ensure DFT timing closure and coverage targets.
• Support post-silicon bring-up, ATE pattern generation, and silicon debugging.

Kenntnisse

DFT methodology

Leadership

Tools

Siemens Tessent

Synopsys DFTMAX

Synopsys TetraMAX

Cadence Modus

Jobbeschreibung

We are Hiring: Senior DFT Engineer (6+ Years Experience)

Role: Senior DFT (Design for Test) Engineer

Experience: 6+ Years

Locations: Bangalore | Hyderabad | Chennai

Notice Period: Immediate to 15 Days (Mandatory)

Key Responsibilities:

• Lead and execute end-to-end DFT flow across complex SoC/ASIC designs.
• Implement Scan Insertion, ATPG (Stuck-at, At-speed/Transition), MBIST, and Boundary Scan (IJTAG / IEEE 1149.1 / 1500 / 1687).
• Conduct Gate-Level Simulations (GLS) with SDF back-annotation and resolve timing/simulation failures.
• Work closely with physical design, synthesis, and STA teams to ensure clean DFT timing closure and coverage target achievement.
• Support post-silicon bring-up, ATE pattern generation, and debug on silicon.

Key Qualifications:

• Experience: 6+ years of hands-on expertise in core DFT methodology and implementation.
• Tools: Proficiency in industry-standard DFT tools (Siemens Tessent, Synopsys DFTMAX/TetraMAX, or Cadence Modus).
• Technical Domain: Scan Compression, MBIST, ATPG, BSDL, IJTAG, and Silicon Debug.
• Notice Period: Immediate joiners or candidates with up to 15 days notice period.