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eInfochips in Ahmedabad, India, is seeking a Senior Engineer RTL Design to drive RTL development for ASIC/FPGA and own front-end design flow from spec to RTL/Netlist. You will code RTL, perform lint and CDC checks, and collaborate with hardware teams on system-level designs.
Typical qualification includes 5–7 years of related experience and a 4-year degree; advanced degrees preferred. The role offers full-time employment at a recognized engineering services company in Gujarat.
Senior Engineer RTL Design
Typically requires 5-7 years of related experience with a 4 year degree; or 3 years and an advanced degree; or equivalent work experience.
IN-GJ-Ahmedabad, India-Aryan Bld-2 (eInfochips)
Full time
Engineering Services