PD Engineer

Cortex Consultants LLC; Bengaluru Urban; On-site; INR 1,200,000 - 1,800,000; Full time

Job summary

A leading semiconductor consultancy in Bengaluru seeks a Physical Design Engineer with over 7 years of experience in ASIC physical design and static timing analysis. The role involves performing floorplanning, placement, CTS, and optimization for ASIC blocks, as well as driving timing closure across multiple corners. Expertise in EDA tools like Synopsys PrimeTime and Cadence Innovus is essential. This position offers opportunities to work on advanced technology nodes and collaborate with various teams to deliver high-performance designs.

Qualifications

• Strong experience in ASIC Physical Design and STA (7+ years).
• Hands-on experience with EDA tools.
• Expertise in timing closure and MCMM analysis.

Responsibilities

• Perform floorplanning, placement, CTS, routing, and optimization for ASIC blocks.
• Drive timing, power, and area optimization throughout the physical design flow.
• Analyze and fix setup, hold, and clock-related timing violations.

Skills

ASIC Physical Design

Static Timing Analysis

Timing Closure

Low Power Design Techniques

Eda tools

Tools

Synopsys PrimeTime

Cadence Innovus

Synopsys ICC2

Job description

Role: Physical Design Engineer

Location: Bangalore / Coimbatore

Experience: 7+ Years

Key Responsibilities

Physical Design

• Perform floorplanning, placement, clock tree synthesis (CTS), routing, and optimization for ASIC blocks.
• Drive timing, power, and area optimization throughout the physical design flow.
• Work closely with RTL, synthesis, and DFT teams to ensure design readiness.

Static Timing Analysis (STA)

• Perform block-level and full-chip STA using industry-standard tools.
• Analyze and fix setup, hold, and clock-related timing violations.
• Perform timing sign-off checks including OCV, MCMM, and path-based analysis.

Timing Closure

• Drive timing closure across multiple corners and modes (MCMM).
• Debug and resolve timing violations, congestion, and power issues.
• Collaborate with backend and front-end teams to meet timing and performance targets.

Sign-Off Activities

• Handle timing sign-off, physical verification, and power analysis.
• Work with sign-off tools for DRC, LVS, IR drop, and EM analysis.
• Ensure design meets foundry sign-off requirements.

Required Skills

• Strong experience in ASIC Physical Design and STA (7+ years)
• Hands-on experience with EDA tools, such as:
  • Synopsys PrimeTime
  • Cadence Innovus
  • Synopsys ICC2
• Expertise in timing closure and MCMM analysis
• Good understanding of low power design techniques
• Experience in advanced technology nodes (16nm / 7nm / 5nm preferred)