Senior Engineer IP

Quest Global; Bengaluru; On-site; INR 1,800,000 - 2,400,000; Full time

Job summary

Quest Global in Bengaluru is seeking an experienced ASIC verification engineer to verify design, architecture and memory subsystems using advanced methodologies. You'll verify ASIC blocks, develop test plans and verification infrastructure, and collaborate with RTL designers and cross-functional teams.

You will build reusable models, monitors, and scoreboards, perform coverage-driven closure, identify gaps, and participate in design and verification plan reviews to ensure feature completeness

Qualifications

• Experience in verifying ASIC designs and architectures.
• Proficiency in verification methodologies and test planning.
• Ability to identify verification gaps and drive closure through tests.

Responsibilities

• Verify ASIC design, architecture, and micro-architecture of memory subsystems.
• Develop test plans, tests, and verification infrastructure for complex IPs/sub-systems.
• Build reusable bus functional models, monitors, checkers, and scoreboards.
• Perform coverage-driven verification closure with architects, designers, and verification teams.
• Collaborate with RTL designers and cross-functional teams to understand design intent.
• Identify coverage holes, develop targeted tests, and track progress to closure.
• Participate in specification reviews, design reviews, and verification plan reviews.

Skills

ASIC verification

Memory subsystems verification

Test plans & verification infra

Coverage-driven verification

RTL collaboration

Job description

• in IP/Sub-system GLS and Low-Power, PCIe experience would be an add-on.
• Verifying ASIC design, architecture, and micro-architecture of memory sub-systems/units using advanced verification methodologies.
• Developing test plans, tests, and verification infrastructure for complex IPs/sub-systems.
• Building reusable bus functional models, monitors, checkers, and scoreboards following coverage-driven verification methodology.
• Performing functional coverage-driven verification closure and working with architects, designers, and verification teams.
• Collaborating with RTL designers, architects, and cross-functional teams to understand design intent and identify verification gaps.
• Identifying coverage holes, developing targeted tests, and tracking progress to closure.
• Participating in specification reviews, design reviews, and verification plan reviews.