Senior Hardware Verification Engineer

NXP Semiconductors; Hyderabad; On-site; INR 1,000,000 - 1,500,000; Full time

Job summary

A leading semiconductor company in Hyderabad is searching for a Senior ASIC Hardware Verification Engineer. This role involves defining verification strategies, architecting UVM-based testbenches, and ensuring comprehensive coverage closure before design tape-out. Candidates should have experience with SystemVerilog and strong debugging skills. The successful candidate will also provide mentorship to junior engineers and collaborate closely with RTL designers for successful verification outcomes.

Qualifications

• Experience in architecting UVM-based testbenches.
• Strong background in functional verification of digital designs.
• Ability to mentor junior engineers in verification processes.

Responsibilities

• Define and document the verification plan including scenarios and models.
• Architect and implement scalable verification environments.
• Develop constrained-random stimulus and directed tests.
• Root-cause hardware failures by analyzing waveforms.
• Drive coverage to 100% using refined stimulus.

Skills

SystemVerilog

UVM

Verification strategy

Debugging skills

Formal Verification

Tools

JasperGold

Palladium

Zebu

Job description

The Senior ASIC Hardware Verification Engineer is responsible for the end-to-end functional verification of complex digital designs (IP, Subsystem, or SoC). You will architect advanced UVM-based testbenches, define exhaustive verification plans, and lead the "coverage closure" process to ensure the design meets all architectural specifications before tape-out.

Responsibilities

• Verification Strategy: Define and document the verification plan (vPlan), including test scenarios, checkers, and functional coverage models.
• Testbench Architecture: Architect and implement scalable, reusable verification environments using SystemVerilog and UVM.
• Advanced Stimulus: Develop constrained-random stimulus and directed tests to stress-test corner cases of the micro-architecture.
• Debugging: Root-cause complex hardware failures by analyzing waveforms (VPD/FSDB) and collaborating with RTL designers.
• Coverage Closure: Drive functional and code coverage to 100%, utilizing exclusions and refined stimulus to reach uncovered logic.
• Performance & Power: Verify throughput, latency, and power-aware (UPF/CPF) features of the silicon.
• Mixed-Methods: Integrate Formal Verification (JasperGold/VC Formal) for control logic and Hardware Emulation (Palladium/Zebu) for long-latency system tests.
• Mentorship: Provide technical leadership to junior engineers and perform code reviews for testbench components.