Senior Design Verification Engineer (Test Bench)

leadIC Design Pvt Ltd; Bengaluru; On-site; INR 2,800,000 - 5,200,000; Full time

Job summary

leadIC Design Pvt Ltd in Bengaluru seeks a seasoned Verification Engineer to own functional verification for a high‑performance ASIC. You will collaborate with RTL and architecture teams to build verification environments, test plans, and coverage strategies that prove the design matches spec before silicon.

You will verify blocks across a multi‑core vector processor, develop UVM testbenches, write SVA assertions, and drive regression ownership with scripting in Python or TCL.

Qualifications

• Bachelor's or higher in engineering with a strong ASIC/SoC verification focus.
• Hands-on experience with SystemVerilog, UVM, and SVA assertions.
• Proficiency in RTL verification methodologies and debugging complex subsystems.

Responsibilities

• Verify RTL blocks for a multi-core vector processor including datapath and pipelines.
• Develop UVM-based testbenches for interconnects, DMA engines, and NICs.
• Create constrained-random tests for ISA opcodes and data types.
• Write SVA assertions for protocol compliance across AXI4/PCIe and bus fabrics.
• Debug RF failures and drive coverage closure with RTL engineers.
• Build regression suites and automate test generation with Python/TCL.

Skills

RTL verification

SystemVerilog

UVM

Debugging

Education

B.E./B.Tech in ECE/EE

Tools

VCS

Xcelium

Questa

Verdi

SimVision

Python

TCL scripting

Job description

We are building a high-performance signal processing ASIC — a multi-core vector processor with a custom ISA, targeting defense, 5G, and test & measurement markets. As a Verification Engineer, you will own functional verification for major subsystems of the chip, from testbench architecture through coverage closure. You will work closely with RTL designers and the architecture team to build the verification environments, assertions, and test plans that prove the design matches spec before it goes to silicon.

Responsibilities

• Verify RTL blocks across custom multi-core vector processor — execution units, register files, datapath pipelines, and arithmetic units (integer, fixed-point, floating-point, complex)
• Develop UVM-based SystemVerilog testbenches for the on-chip network, switch fabric, PCIe endpoint, DMA engines, and inter-core synchronization engine
• Write directed and constrained-random test cases targeting custom ISA opcodes, data types, and pipeline hazard scenarios
• Write SVA assertions for protocol compliance across AXI4-Lite bus fabric, credit-based flow control, and virtual channel logic
• Verify clock domain crossings — async FIFOs, gray-code pointers, 2FF synchronizers — across all subsystem boundaries
• Verify the RISC-V system management controller — boot flow, reset sequencing, phased initialization, and mode switching
• Drive functional and code coverage closure across all execution unit opcodes and supported data types
• Debug RTL failures across the full design hierarchy — waveform tracing, root-cause analysis, and tracking to resolution with RTL engineers
• Build and maintain regression suites for multi-core coordination, barrier logic, and event distribution scenarios
• Automate test generation and regression analysis using Python or TCL scripting

Requirements

• 7+ years of RTL verification experience in ASIC or SoC environment
• Strong SystemVerilog and UVM — testbench architecture, sequences, scoreboards, monitors, functional and code coverage
• SVA assertion writing from architecture specifications — not just consuming existing assertions
• Protocol knowledge — AXI4, AHB, APB; PCIe TLP handling a strong plus
• Hands‑on with simulation tools — VCS, Xcelium, or Questa
• Strong debugging skills — comfortable tracing failures across deep design hierarchy in Verdi or SimVision
• Understanding of processor pipelines — hazard detection, data forwarding, multi‑cycle operations
• Python or TCL scripting for regression automation and test generation
• Ability to work independently from a detailed architecture specification

Nice to Have

• Formal verification — JasperGold, VC Formal, or Questa Formal for exhaustive property checking on arithmetic units and control logic
• PCIe endpoint or NoC verification — TLP handling, credit flow control, virtual channels
• RISC‑V processor verification background