Senior Engineer II - Design

Microchip Technology Inc.; Chennai District; On-site; INR 1,200,000 - 1,800,000; Full time

Job summary

Microchip Technology Inc. in Chennai seeks an experienced STA Engineer with 6 years in VLSI timing verification to drive timing closure across complex SoC/IP designs.

You will collaborate with RTL, Physical Design, DFT, and Signoff teams to ensure high-performance, power-efficient silicon, implement STA constraints, and support ECOs.

The role emphasizes strong analytical and communication skills, and familiarity with Tcl/Perl/Python scripting for constraint automation.

Qualifications

• Bachelor’s or master’s degree in Electronics, Electrical Engineering, VLSI, or related field.
• 3–5 years of hands-on experience in Static Timing Analysis for ASIC/SoC designs.
• Experience with industry-standard STA tools such as PrimeTime and Tempus.
• Good knowledge of synthesis and physical design flow.
• Familiarity with scripting languages such as Tcl, Perl, or Python.
• Strong analytical, communication, and teamwork skills.
• Knowledge of signal integrity and noise analysis.

Responsibilities

• Perform block-level and full-chip Static Timing Analysis (STA) for ASIC/SoC designs.
• Work on timing closure during synthesis, place-and-route, and signoff stages.
• Develop and maintain STA constraints including SDC creation and validation.
• Collaborate with Physical Design and RTL teams to optimize timing, area, and power.
• Support ECO implementation for timing closure.

Skills

Analytical skills

Communication skills

Teamwork

Education

Bachelor’s or Master’s degree in Electronics/Electrical Engineering/VLSI

Tools

PrimeTime

Tempus

Job description

Job Description

We are looking for a skilled and motivated Static Timing Analysis (STA) Engineer with 6 years of experience in VLSI design and timing verification. The candidate will be responsible for timing closure activities across complex SoC/IP designs and will work closely with RTL, Physical Design, DFT, and Signoff teams to ensure high-performance and power‑efficient silicon implementation.

Key Responsibilities

• Perform block‑level and full‑chip Static Timing Analysis (STA) for ASIC/SoC designs.
• Work on timing closure during synthesis, place‑and‑route, and signoff stages.
• Develop and maintain STA constraints including SDC creation and validation.
• Collaborate with Physical Design and RTL teams to optimize timing, area, and power.
• Support ECO implementation for timing closure.

Requirements/Qualifications

• Bachelor’s or master’s degree in Electronics, Electrical Engineering, VLSI, or related field.
• 3‑5 years of hands‑on experience in Static Timing Analysis for ASIC/SoC designs.
• Strong understanding of digital design fundamentals and timing concepts.
• Experience with industry‑standard STA tools such as PrimeTime, Tempus.
• Good knowledge of synthesis and physical design flow.
• Familiarity with scripting languages such as Tcl, Perl, or Python.
• Strong analytical, communication, and teamwork skills.
• Knowledge of signal integrity and noise analysis.

Travel Time

No Travel