Senior Engineer - Design Verification

1840 Micron Tech. OP India LLP; Hyderabad; On-site; INR 800,000 - 1,200,000; Full time

Job summary

1840 Micron Tech. OP India LLP is looking for a Verification Engineer in Hyderabad. The role involves contributing to new product opportunities by aiding in verification activities for DRAM design, leveraging AI-based tools, and improving debug efficiency. Candidates should have hands-on experience in SV, UVM based verification and a good understanding of digital/mixed signal circuits.

The verification engineer will develop test cases, collaborate with cross-functional teams, and utilize industry-standard tools for simulation and verification. A collaborative approach and a desire to work in a dynamic environment are essential.

Qualifications

• Hands on experience in SV, UVM based Verification.
• Good scripting skills using Perl, Python is a plus.
• Good understanding of digital / mixed signal circuits.

Responsibilities

• Contribute to the development of new product opportunities.
• Improve debug efficiency across simulation and silicon learning loops.
• Provide verification support by simulating and analyzing designs.

Skills

SV, UVM based Verification

Scripting skills (Perl, Python)

Digital / mixed signal circuits understanding

Tools

Virtuoso

Xcellium

Simvision

vsim

Waveview

Finseim

Hspice

Job description

Key Responsibilities

• Contribute to the development of new product opportunities by assisting with the overall Verification Activities of DRAM Design.
• Actively leverage AI‑based tools, agentic workflows, and automation frameworks to accelerate verification cycle time.
• Assist in Test‑Case/TB and various other components required for DRAM Design Verification.
• Improve debug efficiency across simulation and silicon learning loops.
• Provide verification support to design projects by simulating, analyzing, and debugging pre‑silicon block level/full chip designs.
• Develop Test cases/Stimulus to increase the functional coverage for all DRAM and emerging memory architectures and features.
• Develop and maintain test benches / test vectors using simulation tools and run regressions for coverage analysis and improvements using Agentic AI Flow.
• Collaborate with CAD, EDA, and software teams to integrate AI‑driven flows into simulation, verification, and design sign‑off environments and contribute to cross‑group communication to work towards standardization and group success.

Required Qualifications

• Hands on experience in SV, UVM based Verification.
• Good scripting skills using Perl, Python is a plus.
• Good understanding of digital / mixed signal circuits and experience in digital / mixed signal Verification.
• Understand the usage of industry standard tools like Virtuoso, Xcellium, Simvision, vsim, Waveview, Finseim, Hspice and Micron‑specific simulators.

EEO Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.