SR ENGINEER, DDEG DESMETH DFT

1840 Micron Tech. OP India LLP; Hyderabad; On-site; INR 800,000 - 1,200,000; Full time

Job summary

1840 Micron Tech. OP India LLP in Hyderabad is seeking a candidate for developing verification infrastructure for DFT test modes functionality. The role involves collaboration with international teams and enhancing verification methodologies.

Applicants should have experience in creating test benches using System Verilog, along with strong analytical skills. A commitment to promoting diversity and inclusion is essential, as all qualified applicants will receive consideration regardless of their backgrounds.

Qualifications

• Experience in developing verification infrastructure and environments.
• Proficient in System Verilog and UVM.
• Strong analytical and debugging skills.

Responsibilities

• Develop verification infrastructure for DFT test modes functionality.
• Analyze gaps in verification flow and propose solutions.
• Maintain and enhance in-house developed verification programs.

Job description

Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

Responsibilities

• Develop verification infrastructure and environment to verify probe and burn DFT test modes functionality.
• Develop verification infrastructure and environment to port‑over the probe and burn DFT patterns into the verification flow.
• Provide verification support to the DRAM and Emerging Memory Design Engineering teams by simulating, analyzing, and debugging pre‑silicon full‑chip and block‑level designs.
• Develop System Verilog testbench infrastructure (e.g. UVM/Non‑UVM and Constrained Random Verification Methodology).
• Responsible for test plan execution, running regressions, code and functional coverage closure.
• Assist product engineering teams with circuit and simulation support during post‑silicon validation phase.
• Analyze gaps within the verification flow and methodology and provide solutions to address them, improve debug efficiency across simulation and silicon learning loops.
• Develop, run, and maintain verification test benches and vectors using industry standard and in‑house developed programs.
• Write test patterns/vectors and monitors to enhance the functional coverage for all DRAM and Emerging Memory architectures and features.
• Automate the collection of simulation data through writing software scripts to improve efficiency.
• Maintain and enhance in‑house developed verification programs and tools.
• Collaborate closely with international colleagues to develop new verification methodologies and strategies to take on future challenges in DRAM and Emerging Memory design.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.