Design Verification Engineer

1840 Micron Tech. OP India LLP; Hyderabad; On-site; INR 800,000 - 1,500,000; Full time

Job summary

1840 Micron Tech. OP India LLP is hiring for a role focused on functional verification within Hyderabad, India. The ideal candidate will take ownership of executing verification for block‑level and full‑chip designs, develop verification plans, and maintain test strategies based on design specifications.

Looking for someone experienced in SystemVerilog / UVM, capable of mentoring junior engineers and collaborating across global teams to enhance verification methodologies. Strong focus on achieving coverage closure and utilizing AI tools for efficient execution is key.

Responsibilities

• Own and execute functional verification for block‑level and full‑chip designs from specification through tape‑out.
• Develop, execute, and maintain verification plans, test strategies, and coverage models based on design specifications.
• Architect, develop, and maintain SystemVerilog / UVM‑based testbenches, test vectors, and assertions.
• Run directed and constrained‑random simulations and debug functional failures to root cause.
• Drive coverage closure and identify verification gaps.
• Work closely with design engineers on RTL, review specifications, and resolve design issues.
• Provide verification status updates and risk assessments to project stakeholders.
• Collaborate with cross‑functional teams across global sites.
• Contribute to the development and improvement of verification tools.
• Provide verification support by simulating and debugging pre‑silicon full chip designs.
• Develop Test cases/Stimulus for functional coverage of DRAM and emerging memory architectures.
• Participate in developing verification methodology for advanced DRAM products.
• Co‑work with international colleagues on new verification flows.
• Mentor and guide junior engineers, providing technical leadership.
• Use Micron‑approved AI tools to enhance verification activities.

Job description

Responsibilities

• Own and execute functional verification for block‑level and full‑chip designs from specification through tape‑out
• Develop, execute, and maintain verification plans, test strategies, and coverage models based on design specifications
• Architect, develop, and maintain SystemVerilog / UVM‑based testbenches, test vectors, and assertions
• Run directed and constrained‑random simulations and debug functional failures to root cause
• Drive coverage closure (functional, code, and assertion coverage) and identify verification gaps
• Work closely with design engineers to understand RTL, review specifications, and resolve design issues
• Provide verification status updates, summaries, and risk assessments to project stakeholders
• Collaborate with cross‑functional teams including design, validation, product engineering, and methodology teams across global sites
• Contribute to the development and improvement of verification tools, flows, and methodologies
• Provide verification support to design projects by simulating, analyzing and debugging pre‑silicon full chip designs
• Develop Test cases/Stimulus to increase the functional coverage for all DRAM and emerging memory architectures and features
• Participate in developing verification methodology and verification environments for advanced DRAM and emerging memory products
• Co‑work with international colleagues on developing new verification flows to take on the challenges in DRAM and emerging memory design
• Mentor and guide junior engineers, providing technical leadership within the verification team
• Effective and compliant use of Micron‑approved AI tools to augment verification activities, improve execution efficiency, and support continuous improvement

EEO Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.