Engineer, DEG Mobile DRAM Verification

1840 Micron Tech. OP India LLP; Hyderabad; On-site; INR 1,000,000 - 1,500,000; Full time

Job summary

1840 Micron Tech. OP India LLP in Hyderabad is seeking a Senior Verification Engineer responsible for exclusive ownership of verification and analysis of advanced full-chip gate level custom designs. The role involves collaborating with global teams and leveraging cutting-edge memory technologies like DDR5 and DDR6.

The ideal candidate will have experience in SystemVerilog, gate-level simulations, and will actively contribute to developing verification environments. A Bachelor’s or Master’s degree in Electronics Engineering is required.

Qualifications

• Exposure to gate-level simulations (with delays) and logic schematic analysis.
• Experience in timing analysis: setup/hold and critical data path timing.
• Experience using AI-assisted tools to improve verification productivity.

Responsibilities

• Guide and set the direction for the verification effort within your expertise.
• Provide verification support to design projects by simulating, analyzing, and debugging pre-silicon designs.
• Develop test cases and stimulus to increase functional coverage for all memory architectures.

Skills

Good communication skills

Analytical capability for complex CMOS designs

Proficiency with Verilog simulations

Education

Bachelor’s or Master’s degree in Electronics Engineering or related field

Tools

SystemVerilog

PLI coding

UVM test bench development

Job description

Senior Verification Engineer

Job summary: Exclusive ownership of verification and end-to-end analysis of sophisticated full-chip gate level custom designs, spanning memory technologies such as DDR5, LPDDR5, DDR6, and LPDDR6, operating at high speeds up to 9600MT/s. Collaborate with global design and verification teams, leveraging advanced low power and power‑management technologies.

Responsibilities

• Guide and set the direction for the verification effort within your expertise for the team’s projects.
• Provide verification support to design projects by simulating, analyzing, and debugging pre‑silicon full-chip designs.
• Develop test cases and stimulus to increase functional coverage for all DRAM and emerging memory architectures and features.
• Participate in developing verification methodology and environments for sophisticated products.
• Co‑work with international colleagues on new verification flows to address design challenges.
• Develop and maintain test benches and vectors using simulation tools, run regressions for coverage analysis and improvements.
• Identify verification pain points suitable for AI‑based automation and collaborate with cross‑functional teams to deploy scalable solutions.

Core Requirements

• Good communication skills and ability to work well in a team.
• Exposure to gate-level simulations (with delays) and logic schematic analysis.
• Analytical capability for complex CMOS and/or gate-level circuit designs.
• Proficiency with Verilog simulations.

Qualifications & Skills

• Experience in SystemVerilog, PLI coding.
• Experience in UVM test bench development.
• Experience in DRAM, SRAM or other memory-related fields.
• Experience in timing analysis: setup/hold and critical data path timing.
• Experience using AI‑assisted tools to improve verification productivity, with a strong emphasis on correctness, validation, and responsible use of enterprise‑approved AI systems.
• Bachelor’s or Master’s degree in Electronics Engineering or related engineering field.

EEO Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.