Principal Engineer- DEG Layout

1840 Micron Tech. OP India LLP; Bengaluru; On-site; INR 1,800,000 - 3,000,000; Full time

Job summary

1840 Micron Tech. OP India LLP in Bengaluru (Karnataka) seeks an experienced layout designer to develop analog, mixed-signal and digital block layouts for full chip projects. You will use auto-placement and routing tools, participate in LVS/DRC checks and drive on-time delivery with quality governance.

The role requires leadership in planning, estimation and guiding sub-teams, with effective coordination with global engineering teams and a push to reduce layout effort through AI-enabled methods.

Qualifications

• Responsible for layout design and development of critical analog, mixed-signal, custom digital block, standard cells and full chip level.
• Perform layout verification such as LVS, DRC, Antenna, Shield, Matching, Latch up, EM IR Totem checks, quality checks and documentation.
• Develop digital block layouts using auto-placement and route tools.
• Possess basic understanding of skill coding and automation.
• Ensure on-time delivery of block-level layouts with acceptable quality.
• Demonstrate leadership in planning, area/time estimation, scheduling, delegation and execution to meet project schedule and breakthroughs in a multi-project environment.
• Guide team members in the execution of sub-block-level layouts and review their work.
• Effectively communicate with global engineering teams to assure the success of layout projects.
• Reduce layout effort through AI utilization.

Responsibilities

• Responsible for layout design and development of critical analog, mixed-signal, custom digital block, standard cells and full chip level.
• Perform layout verification such as LVS, DRC, Antenna, Shield, Matching, Latch up, EM IR Totem checks, quality checks and documentation.
• Develop digital block layouts using auto-placement and route tools.
• Possess basic understanding of skill coding and automation.
• Ensure on-time delivery of block-level layouts with acceptable quality.
• Demonstrate leadership in planning, area/time estimation, scheduling, delegation and execution to meet project schedule and breakthroughs in a multi-project environment.
• Guide team members in the execution of sub-block-level layouts and review their work.
• Effectively communicate with global engineering teams to assure the success of layout projects.
• Reduce layout effort through AI utilization.

Skills

Layout design

Digital/Analog

Layout verification

Leadership

Communication

Tools

ECAD tools

Job description

Role and Responsibilities

• Responsible for layout design and development of critical analog, mixed‑signal, custom digital block, standard cells and full chip level.
• Perform layout verification such as LVS, DRC, Antenna, Shield, Matching, Latch up, EM IR Totem checks, quality checks and documentation.
• Develop digital block layouts using auto‑placement and route tools.
• Possess basic understanding of skill coding and automation.
• Ensure on‑time delivery of block‑level layouts with acceptable quality.
• Demonstrate leadership in planning, area/time estimation, scheduling, delegation and execution to meet project schedule and breakthroughs in a multi‑project environment.
• Guide team members in the execution of sub‑block‑level layouts and review their work.
• Effectively communicate with global engineering teams to assure the success of layout projects.
• Reduce layout effort through AI utilization.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.