Senior Engineer - ASIC Verification

MosChip; Bengaluru; On-site; INR 900,000 - 1,400,000; Full time

Job summary

MosChip in Bengaluru, India, is hiring a verification engineer to develop testbench components for chip/module level using SystemVerilog and C/C++. You will apply UVM and other methodologies to build extendable environments and define verification plans with architects and designers.

The role requires strong debugging skills in software and ASIC hardware, plus proficiency with simulators such as ncVerilog, VCS, Eldo and tools Verdi/Debussy. Scripting in Perl/Tcl/Shell is a plus.

Qualifications

• Experience with SystemVerilog and UVM for testbench development.
• Ability to build extendable verification environments and test-cases.
• Strong debugging skills for software and ASIC hardware.
• Proficiency with simulators and waveform/debug tools.

Responsibilities

• Develop verification testbench components for chip/module level using SystemVerilog and C/C++.
• Use verification methodologies (UVM, OO) to create extendable test benches and test cases.
• Define and execute verification plans with architects, designers, and system engineers.
• Write, debug, and automate regression scripts and environments.
• Incorporate code-coverage, assertions, and cover-groups to improve verification completeness.

Skills

SystemVerilog

C/C++

UVM

Testbench development

Debugging

Scripting (Perl/Tcl/Shell)

Verilog/VHDL concepts

Tools

ncVerilog

VCS

Eldo

Verdi/Debussy

Job description

Job Description

• Develop verification testbench components for chip/module level using System Verilog, C/C++.
• Use Verification methodologies (Object oriented, UVM etc) to develop extendable test-bench/test-cases environment.
• Define and execute detailed verification plan from spec working with architects, designers, system engineers.
• Write tests, Debug tests, automate regression scripts and regression environment.
• Incorporate code-coverage, functional coverage, assertions, cover-groups etc to achieve 100% verification completeness prior to tapeout.
• Organized and creative thinker, motivated, and independent learner who can multitask in a dynamic environment, able to create and implement new solutions where required.
• Excellent debugging skills in both SW and ASIC hardware.
• Must be good in building verification environments preferably using Verilog, System Verilog, UVM, C/C++/PLI etc.
• Proficiency in scripting language like Perl, Tcl/Tk, Shell is a definite plus.
• Experience with simulators like ncVerilog (Incisive), VCS, Eldo and debug tools like Verdi/Debussy.
• Good understanding of latest formal verification techniques, assertions, properties is a plus.
• Understanding or prior experience with Industry standard protocols like USB/SPI/SATA/Ethernet/DisplayPort/SRIO/DDR/PCIE/DDR4/LPDDR4/DFI etc is a definite plus.
• Understanding or Prior Experience in ARM/Tensilica Processor platforms is a definite plus.
• Good written and oral communication skills. Ability to clearly document plans.
• ability to interface with different teams and prioritize work based on project needs.