Senior Design Verification Engineer

Mulya Technologies; Bengaluru; On-site; INR 2,500,000 - 4,500,000; Full time

Job summary

Mulya Technologies in Bengaluru, India seeks a seasoned ASIC verification engineer to own verification delivery across complex SoC blocks. You will implement test benches in UVM/SystemVerilog, run RTL and gate-level regressions, and report DV metrics with bug tracking and coverage analysis.

You should have 5–10+ years of silicon IC verification, strong UVM, and fluency with Perl/Python/Tcl for automation. Collaboration with design teams across global sites is required.

Qualifications

• BS or MS in Computer Science or Electrical Engineering.
• 5-10+ years of silicon IC verification experience.
• Strong UVM experience across full chip verification.
• Knowledge of ARMv8, memory coherence, interconnect.
• Experience with scripting languages: Perl, Python, Tcl.
• Experience with RTL, gate-level verification and regression.

Responsibilities

• Develop test benches in UVM and SystemVerilog.
• Run regressions at RTL and gate level.
• Generate DV metrics and report bugs and coverage.
• Work with design and verification teams across sites.
• Lead debugging and troubleshooting in real time.

Skills

UVM

SystemVerilog

Verilog

RTL verification

C/C++

Python

Perl

Tcl

Debugging

ARMv8

Education

BS or MS in Computer Science or Electrical Engineering

Tools

Emulation

Formal verification tools

Gate-level verification

IP validation

Job description

Top 100 Global Semiconductor MNC in the world

Description

We are a innovative enterprise that designs, develops, and delivers System-on-Chip products to customers worldwide. The company is focused on AR/VR, imaging, networking, storage, and other dynamic technologies that drive today’s leading-edge applications. We combine world-class expertise, experience, and an extensive IP portfolio to provide exceptional solutions and ensure a better quality of experience for customers. Founded in 2015, We are headquartered in Japan, and have offices in Japan, Asia, United States and Europe to lead its product development and sales activities.

Primary Responsibilities Inclu

de:

Responsible for all aspects of verification methodology employed and for ensuring the application of uniform standards and adoption of best practi

ces.Work and liaison with other Design Verification teams within our customer sites to identify holes in the design verification flow and implement corrective act

ion.Overall, responsible for verification of ASIC designs To include such things

as:Design Verification – Implement test benches in UVM and Sytem Verilog, run regressions at RTL and gate level, generate and report DV metrics with respect to bug tracking and code coverage,debug failures and providefeedback to the designt

eam.Responsible for oversight and completion of debugging problems and troubleshooting in Real Time. This includes being responsible forDebugging Designs for High throughput, Low Latency of Pipeline and DynamicPower Management at full system le

vel.Setup Verification Regression suites at RTL Level & Corresponding NetlistLevel after Synthesis to test any/all Cornercase conditi

ons.Work closely with design team to ensure the Company is meeting design requirements for projects. This may include: review of specifications, understanding chip architecture, developing tests & coverage plans, and defining methodology & test benc

hes.Work closely with Custom SoC department to provide great customer service to our clients and the projects at hand. Support, encourage and drive timelyand accurate deliverables with customers withinsched

ules

Necessary Qualificat

ions:

BS or MS in Computer Science or Electrical Engine

ering.5-10+ years of industry experience bringing silicon ICs into high volume produ

ction.Must have strong experience wit

h UVM.Must have a full chip verification expe

rienceExperience of leading a single pr

oject.Knowledge of industry standard interfaces. Extensive Familiarity with Verilog, Simulation tools & demonstrated ability to debug Problems & Troubleshoot in Rea

lTime.Sound knowledge of ARMv8, interconnect, memory coherence and memory archite

cturesFamiliarity with Formality & most popular Verification Tools. (Key knowledge should include such topics as: IP validation, Gate level verification, FPGA Validation, Emulation, Silicon Validation, Reference Board bring up verification, Silicon Bring up, DFx, Low Power Verific

ation)Expertise in writing Perl / Python , awk, sed & Common Scripts to automate the Verification Tasks for CPU plus all Chip peripherals – USB, PCIe, MIPI, SDIO, PCI E & DDR Controllers.Advanced knowledge of ASIC design and verification flow including RTL design, simulation, test bench development, regression, equivalence checking, timing analysis, scan insertion and test pattern gene

ration

Experience with low-level programming of systems in

C/C++.Experienced in writing scripts in languages such as Perl, Python, an

d Tcl.Functional understanding of constrained random verification process, functional coverage, and code coverage.Low power verification UPF

Team player with excellent communication skills and the desire to take on diverse chall

Other Qualifications:

Good knowledge of low power camera and imaging systems is a plus

Experience with formal verification tools is

Familiarity with ARM architecture

Familiarity with scripting/programming with Perl/Python, Tcl, C/C++