Senior Design Verification Engineer

Mulya Technologies; Bengaluru; On-site; INR 1,000,000 - 1,500,000; Full time

Job summary

A semiconductor company located in Bengaluru, India is seeking a Verification Engineer to ensure high standards in ASIC design verification using UVM. The ideal candidate will have 5-10 years of experience, a degree in Computer Science or Electrical Engineering, and strong debugging skills. This full-time position offers the opportunity to collaborate with cross-functional teams and work on cutting-edge technologies.

Qualifications

• 5-10+ years of industry experience bringing silicon ICs into high-volume production.
• Strong experience with UVM and full-chip verification.
• Proficiency in writing scripts in Perl / Python, awk, sed.

Responsibilities

• Responsible for all aspects of verification methodology employed.
• Verify ASIC designs including test benches in UVM and SystemVerilog.
• Collaborate with the Custom SoC department to provide excellent customer service.

Skills

UVM

Verilog

Python

C/C++

Debugging

Team collaboration

Education

BS or MS in Computer Science or Electrical Engineering

Tools

Simulation tools

Formal verification tools

Job description

Overview

We are a innovative enterprise that designs, develops, and delivers System-on-Chip products to customers worldwide. The company focuses on AR/VR, imaging, networking, storage, and other dynamic technologies that drive today’s leading-edge applications. Founded in 2015, we are headquartered in Japan, and have offices in Japan, Asia, United States and Europe to lead its product development and sales activities.

Responsibilities

• Responsible for all aspects of verification methodology employed and for ensuring the application of uniform standards and adoption of best practices.
• Work and liaison with other Design Verification teams within our customer sites to identify holes in the design verification flow and implement corrective actions.
• Verify ASIC designs, including: design verification – implement test benches in UVM and SystemVerilog, run regressions at RTL and gate level, generate and report DV metrics with respect to bug tracking and code coverage, debug failures and provide feedback to the design team.
• Oversee and complete debugging problems and troubleshooting in real time, including debugging designs for high throughput, low latency of pipelines, and dynamic power management at full system level.
• Set up verification regression suites at RTL level and corresponding netlist level after synthesis to test corner-case conditions.
• Work closely with the design team to ensure the company is meeting design requirements for projects, including review of specifications, understanding chip architecture, developing tests and coverage plans, and defining methodology and test benches.
• Collaborate with the Custom SoC department to provide excellent customer service to clients and projects, supporting timely and accurate deliverables within schedule.

Qualifications

• BS or MS in Computer Science or Electrical Engineering.
• 5-10+ years of industry experience bringing silicon ICs into high-volume production.
• Strong experience with UVM and full-chip verification.
• Experience leading a single project and coordinating verification efforts.
• Knowledge of industry standard interfaces. Extensive familiarity with Verilog, simulation tools, and ability to debug problems in real time.
• Sound knowledge of ARMv8, interconnect, memory coherence and memory architecture.
• Familiarity with Formal verification tools and topics such as IP validation, gate-level verification, FPGA validation, emulation, silicon bring-up, DFx, and low-power verification.
• Proficiency in writing scripts in Perl / Python, awk, sed, and other languages to automate verification tasks for CPUs and chip peripherals (USB, PCIe, MIPI, SDIO, PCIe, DDR controllers).
• Advanced knowledge of ASIC design and verification flow including RTL design, simulation, test bench development, regression, equivalence checking, timing analysis, scan insertion and test pattern generation.
• Experience with low-level programming of systems in C/C++. Experience writing scripts in Perl, Python, and Tcl. Functional understanding of constrained-random verification, functional and code coverage, and low-power verification UPF.
• Team player with excellent communication skills and ability to handle diverse challenges.
• Good knowledge of low-power camera and imaging systems is a plus. Familiarity with ARM architecture and formal verification tools is beneficial.

Employment type

• Full-time

Seniority level

• Mid-Senior level