Staff Engineer - ASIC SOC Verification

1840 Micron Tech. OP India LLP; Hyderabad; On-site; INR 1,400,000 - 2,000,000; Full time

Job summary

1840 Micron Tech. OP India LLP in Hyderabad is hiring for a position focused on SoC verification to advance their innovative memory and storage solutions. Candidates must possess a strong background in SOC/IP verification and a minimum of 7 years experience working with SV/UVM methodologies.

The successful applicant will engage in creating verification plans, developing testcases, and automating verification environments. Strong scripting and communication skills are essential.

Qualifications

• Minimum 7+ years of SOC/IP Verification based on SV/UVM.
• Good understanding on Test controller / MBIST / DFT architecture.
• Proven experience in scripting languages such as Python / Perl / TCL.

Responsibilities

• Create SoC Verification plan and develop C/SV/UVM based SoC verification tests.
• Develop flows to automate verification environment development and drive team.
• Interact with Architecture/Design/Tester teams for ASIC test vectors.

Skills

SoC Verification

SV/UVM knowledge

Scripting languages (Python/Perl/TCL)

Problem solving

Communication skills

Education

Bachelors/Masters in Engineering

Tools

ATE/Functional CHAZ vector enablement

Job description

Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

Job Responsibilities

• Create SoC Verification plan and develop C/SV/UVM based SoC verification tests
• Develop understanding on SoC Architecture and Test controller Architecture
• Develop SV / UVM based testcases for Test controller verification, MBIST verification and Functional vectors generation
• Develop SV/UVM monitors to measure performance and improve Verification Environment
• Interact with Architecture/Design/Tester teams to identify ASIC test vectors and functional patterns requirement
• Develop flows to automate verification environment development and drive team
• Involve in Vectors Bring-up activity and support ATE/Tester teams for Functional Characterization

Job Qualifications

• Bachelors/Masters in Engineering.
• Minimum 7+ years of SOC/IP Verification based on SV/UVM.
• Good understanding on Test controller / MBIST / DFT architecture
• Knowledge of industry standard interfaces, such as PCIE, LPDDR*, ONFI/NAND is desired.
• Proven experience in ATE/Functional CHAZ vector enablement in Silicon / Wafers and debug abilities on vectors
• Proven experience in scripting languages such as Python / Perl / TCL
• Solid verification skills in problem solving, constrained random testing, and debugging.
• Good written and oral communication.
• Positive attitude must.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.