Lead Engineer - ASIC Verification

MosChip; Bengaluru; On-site; INR 1,200,000 - 1,800,000; Full time

Job summary

MOSCHIP seeks a verification engineer to develop chip/module level testbenches using SystemVerilog and C/C++. You will apply UVM and OO methodologies to build an extendable verification environment, define plans with architects, write and debug tests, and drive regression with coverage and assertions to ensure tapeout readiness.

Candidate should have strong debugging skills for both software and ASIC hardware, plus experience with common simulators and industry protocols.

Qualifications

• Experience in building verification environments for chip/module level.
• Proficient in SystemVerilog and UVM for testbench development.
• Ability to define verification plans with architects and designers.
• Experience with regression scripting and 100% coverage goals.
• Strong debugging skills in software and ASIC hardware.
• Familiarity with industry protocols like USB, SPI, SATA, Ethernet, PCIe.
• Proficiency with scripting languages: Perl, Tcl, Shell.

Responsibilities

• Develop verification testbench components for chip/module level using SystemVerilog and C/C++.
• Use verification methodologies (OO, UVM) to develop extensible environments.
• Define and execute verification plans from specs with architects and designers.
• Write tests, debug tests, and automate regression scripts and environment.
• Incorporate coverage, assertions, and cover-groups to approach 100% tapeout readiness.
• Collaborate across teams and prioritize tasks in a dynamic setup.

Skills

SystemVerilog

C/C++

UVM

Testbench development

Verification planning

Debugging

Code coverage

Assertions

Perl

Tcl

Shell

ARM/Tensillica

Tools

ncVerilog

VCS

Eldo

Verdi

Debussy

PLI

Job description

Job Description

• Develop verification testbench components for chip/module level using System Verilog, C/C++.
• Use Verification methodologies (Object oriented, UVM etc) to develop extendable test-bench/test-cases environment.
• Define and execute detailed verification plan from spec working with architects, designers, system engineers.
• Write tests, Debug tests, automate regression scripts and regression environment.
• Incorporate code-coverage, functional coverage, assertions, cover-groups etc to achieve 100% verification completeness prior to tapeout.
• Organized and creative thinker, motivated, and independent learner who can multitask in a dynamic environment, able to create and implement new solutions where required.
• Excellent debugging skills in both SW and ASIC hardware.
• Must be good in building verification environments preferably using Verilog, System Verilog, UVM, C/C++/PLI etc.
• Proficiency in scripting language like Perl, Tcl/Tk, Shell is a definite plus.
• Experience with simulators like ncVerilog (Incisive), VCS, Eldo and debug tools like Verdi/Debussy.
• Good understanding of latest formal verification techniques, assertions, properties is a plus.
• Understanding or prior experience with Industry standard protocols like USB/SPI/SATA/Ethernet/DisplayPort/SRIO/DDR/PCIE/DDR4/LPDDR4/DFI etc is a definite plus.
• Understanding or Prior Experience in ARM/Tensillica Processor platforms is a definite plus.
• Good written and oral communication skills. Ability to clearly document plans.
• Ability to interface with different teams and prioritize work based on project needs.