Design Verification Engineer

MediaTek; Bengaluru; On-site; INR 3,000,000 - 6,000,000; Full time

Job summary

MediaTek is seeking a skilled ASIC verification engineer in Bengaluru to contribute to advanced digital and mixed-signal IP verification. The role requires hands-on work with UVM-based methodologies, SystemVerilog, Verilog, and SVA, plus test bench development, simulation, and rigorous coverage goals.

Familiarity with analog IPs and power-aware simulations is a plus. You will collaborate with design and verification teams, drive test plans, and help achieve functional and code coverage

Qualifications

• Experience in ASIC functional verification and testbench development.
• Hands-on verification of digital and mixed-signal IPs preferred.
• Proficiency with UVM, SystemVerilog, Verilog and SVA for assertion-based verification.
• Strong debugging, simulation, and coverage closure skills.
• Knowledge of design verification development process from spec to test plan and test suite.

Skills

UVM-based verification

Verilog

SystemVerilog

SVA

Digital Design

ASIC design process

test bench development

simulation

debugging

coverage closure

Power-aware simulations

Unix/Linux scripting

Python

Perl

Makefile

Version control (Perforce/ClearCase)

SystemC/C/C++

Tools

Perforce

ClearCase

Job description

• Quick learner with strong critical thinking and creative problem-solving skills.
• Solid knowledge in ASIC design process, Digital Design and UVM-based design verification methodologies.
• Proficient on using design and verification languages: UVM, Verilog, System Verilog, and System Verilog Assertions (SVA).
• Proficient on Design Verification tools and techniques, including test bench development, simulation, debugging and coverage closure, etc.
• Knowledge on Design Verification development process, from specification to test plan, to configurable test bench, drivers and checkers development, to test suite building to meet functional and code coverage goals,
• Good ASIC functional verification hands-on work experience, preferably with some verification experience on analog mixed signal IPs or SERDES IPs, such as USB, UFS, PCIe, DDR-PHY, etc.
• Power-aware simulations and gate level simulations is a plus
• Scripting and automation skills: Unix/Linux shell programming, Perl, Python, Makefile, and revision management (e.g., Perforce, ClearCase, etc.) is a plus.
• Knowledge of Analog Mixed-Signal Design Fundamentals and analog behavioral modeling is a plus
• Familiar with programming languages: C, C++, and/or SystemC is a plus.