Senior DV Engineers (UVM/Verliog)

L&T Technology Services; Bengaluru; On-site; INR 3,000,000 - 4,500,000; Full time

Job summary

LTTS is seeking a senior Design Verification engineer in Bengaluru with 7+ years of hands-on experience in StemVerilog/UVM and related verification methods. The role covers IP/SoC verification, UVM environments, and DV infrastructure architecture.

Candidate should have strong experience with ARM/RISC‑V CPU sub-stems, IP/integration verification, and protocols like AMBA, PCIe, DDR, USB and Ethernet, plus scripting and version control skills.

Qualifications

• 7+ years hands-on experience in StemVerilog/UVM methodology.
• 8/10+ hands-on experience in StemVerilog/UVM/OVM based verification for IP/sub-stem/SoC.
• Experience in development of UVM based verification environments from scratch.
• Experience in architecting and implementing Design Verification infrastructure and executing the full verification cycle.
• Experience with verification of ARM/RISC‑V based CPU sub-stems or SoCs.
• Experience with IP or integration verification and protocols like AMBA, PCIe, DDR, USB, Ethernet.
• Experience in E tools and scripting (Python, TCL, Perl, Shell) for verification flows.
• Experience with revision control systems like Mercurial (Hg), Git or SVN.

Responsibilities

• Lead the verification effort for DV projects and drive the full verification cycle.
• Architect and implement verification environments and tool flows for large-scale SoCs.
• Coordinate IP integration and sub-system verification with AMBA/PCIe/DDR/USB/Ethernet protocols.
• Mentor junior engineers and ensure on-time delivery with quality artifacts.

Skills

StemVerilog/UVM

C/C++ verification

IP/SoC verification

UVM environments from scratch

Design Verification infrastructure

ARM/RISC-V CPU verification

IP/integration verification

Scripting: Python, TCL, Perl, Shell

Version control: Hg/Git/SVN

Job description

LTTS is looking for DV engineers with 7+ years of experience for lead role...detailed JD is below mentioned.

8/10+ of hands‑on experience in StemVerilog/UVM methodology and/or C/C++ based verification

8/ 10+ experience in IP/sub‑stem and/or SoC level verification based on StemVerilog UVM/OVM based methodologies

Experience in development of UVM based verification environments from scratch

Experience in architecting and implementing Design Verification infrastructure and executing the full verification cycle

Experience with verification of ARM/RISC‑V based CPU sub‑stems or SoCs

Experience with IP or integration verification along with expertise of protocols like AMBA, PCIe, DDR, USB, Ethernet

Experience in E tools and scripting ( Python, TCL, Perl, Shell) used to build tools and flows for verification environments

Experience with revision control stems like Mercurial (Hg), Git or SVN