Senior DV Engineer

L&T Technology Services; Bengaluru; On-site; INR 1,200,000 - 1,800,000; Full time

Job summary

LTTS in Bangalore is seeking Design Verification Engineers with 5+ years of hands-on experience to define and implement verification plans for IP/SoC, build test benches, and develop functional tests.

You will drive verification closure using UVM/OVM methodologies, debug complex issues, and collaborate with the Design team. Proficiency in StemVerilog, C/C++, scripting, and AMBA/PCIe/DDR/USB/Ethernet is expected.

Qualifications

• Bachelor's or Masters degree in Computer Science, Electronics Engineering or equivalent practical experience
• 5 + of hands‑on experience in StemVerilog/UVM methodology and/or C/C++ based verification
• 5+ experience in IP/sub-stem and/or SoC level verification based on StemVerilog UVM/OVM based methodologies
• Experience in development of UVM based verification environments from scratch
• Experience in architecting and implementing Design Verification infrastructure and executing the full verification cycle
• Experience with verification of ARM/RISC‑V based CPU sub‑stems or SoCs
• Experience with IP or integration verification along with expertise of protocols like AMBA, PCIe, DDR, USB, Ethernet
• Experience in E tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments
• Experience with revision control stems like Mercurial(Hg), Git or SVN

Responsibilities

• Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-stem/SoC level verification
• Develop functional tests based on verification test plan
• Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage
• Debug, root-cause and resolve functional failures in the design, partnering with the Design team

Skills

StemVerilog/UVM

C/C++ verification

IP/SoC verification

UVM/OVM

Debugging

Scripting (Python,TCL,Perl,Shell)

Version control (Git,Hg,SVN)

AMBA, PCIe, DDR, USB, Ethernet

ARM/RISC-V verification

Test bench design

Education

Bachelor's or Master's degree in Computer Science, Electronics Engineering or equivalent practical experience

Tools

Mercurial(Hg)

Git

SVN

Python

TCL

Perl

Shell

Job description

LTTS is hiring for Design Verification Engineers with 5+ Years of experience.

Job Location : Bangalore, India

Detailed JD is as below ::

Job Description DV Positions:

• Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-stem/SoC level verification
• Develop functional tests based on verification test plan
• Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage
• Debug, root-cause and resolve functional failures in the design, partnering with the Design team

Qualifications and Skills for DV Positions:

• Bachelor's or Masters degree in Computer Science, Electronics Engineering or equivalent practical experience
• 5 + of hands‑on experience in StemVerilog/UVM methodology and/or C/C++ based verification
• 5+ experience in IP/sub-stem and/or SoC level verification based on StemVerilog UVM/OVM based methodologies
• Experience in development of UVM based verification environments from scratch
• Experience in architecting and implementing Design Verification infrastructure and executing the full verification cycle
• Experience with verification of ARM/RISC‑V based CPU sub‑stems or SoCs
• Experience with IP or integration verification along with expertise of protocols like AMBA, PCIe, DDR, USB, Ethernet
• Experience in E tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments
• Experience with revision control stems like Mercurial(Hg), Git or SVN