Senior Dv Engineer

Let Technology Services; Bengaluru; On-site; INR 1,800,000 - 3,200,000; Full time

Job summary

LTTS in Bengaluru, India, seeks Design Verification Engineers with 5+ years of hands-on StemVerilog/UVM verification experience. The role focuses on defining verification plans, building test benches, and driving DV closure through robust test and coverage metrics.

Candidates should have a strong background in IP/sub-system/SoC verification, scripting, and experience with ARM/RISC-V CPUs and related interfaces. Come join a high-impact, fast-paced DV team.

Qualifications

• Bachelor's or Master's degree in Computer Science, Electronics Engineering or equivalent practical experience
• 5+ years hands-on StemVerilog/UVM verification
• 5+ years IP/sub-system/SoC verification using StemVerilog/UVM/OVM
• Experience developing UVM-based verification environments from scratch
• Experience architecting Design Verification infrastructure and full verification cycle
• Experience verifying ARM/RISC-V CPU subsystems/SoCs
• Experience with IP or integration verification and protocols (AMBA, PCIe, DDR, USB, Ethernet)
• Experience with E tools and scripting (Python, TCL, Perl, Shell)
• Experience with revision control systems (Mercurial, Git, SVN)

Responsibilities

• Define and implement IP/SoC verification plans
• Build verification test benches for IP/sub-system/SoC verification
• Develop functional tests from verification test plans
• Drive DV to closure using metrics like test plan, coverage
• Debug and root-cause functional failures with Design team

Skills

StemVerilog/UVM

C/C++ verification

UVM environments

DV infrastructure

ARM/RISC-V verification

Education

Bachelor's or Master's in CS/EE

Tools

Git

Mercurial

SVN

Job description

Job DescriptionLTTS is hiring for Design Verification Engineers with 5+ Years of experience. Job Location : Bangalore, India Detailed JD is as below ::

DV Positions

• Define and implement IP/SoC verification plans,
• build verification test benches to enable IP/sub-stem/SoC level verification,
• Develop functional tests based on verification test plan,
• Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage,
• Debug, root-cause and resolve functional failures in the design, partnering with the Design team.

Qualifications and Skills for DV Positions

• Bachelor's or Masters degree in Computer Science, Electronics Engineering or equivalent practical experience
• 5 + of hands-on experience in StemVerilog/UVM methodology and/or C/C++ based verification
• 5+ experience in IP/sub-stem and/or SoC level verification based on StemVerilog UVM/OVM based methodologies
• Experience in development of UVM based verification environments from scratch
• Experience in architecting and implementing Design Verification infrastructure and executing the full verification cycle
• Experience with verification of ARM/RISC-V based CPU sub-stems or SoCs
• Experience with IP or integration verification along with expertise of protocols like AMBA, PCIe, DDR, USB, Ethernet
• Experience in E tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments
• Experience with revision control stems like Mercurial(Hg), Git or SVN