Verification Lead

Mulya Technologies; Bengaluru; On-site; INR 4,200,000 - 6,500,000; Full time

Job summary

Mulya Technologies seeks an experienced DV Lead to own verification of complex blocks, subsystems, or SOCs using SystemVerilog and UVM. The role requires leading a team of engineers and delivering high-quality tests toward coverage goals.

You will drive test plan development, debug across the verification flow, and work on IP/sub-system and SOC level verification using SV/UVM. Bangalore/Hyderabad/Kochi locations are supported.

Qualifications

• 11+ years of hands-on DV experience in System Verilog/UVM.
• Must own and drive verification of a block/subsystem or SOC.
• Experience leading a team of engineers.

Responsibilities

• Own and drive verification of blocks/subsystems/SOC using SV/UVM.
• Lead a team of DV engineers and monitor progress.
• Develop test plans and constrained-random UVM tests to hit coverage goals on time.
• Debug across the verification flow including Gatesims.
• Coordinate IP/sub-system and SOC level verification activities.

Skills

Systemverilog

UVM

SoC

ip verification

PCIE

UCIE

CXL

NVMe

CHI

Ethernet

ROCE

RDMA

DDR7

LPDDR5

HBM

ARM

RISC-V

C

Assembly

power aware

Jasper

Tools

VCS

Verdi

Cadence Xcelium

Simvision

Jasper

Git

Perforce

Clearcase

Job description

DV Lead

Among. The top 4 IT companies, in India ranked by market capitalization and revenue

Bangalore /Hyderabad / Kochi

DV lead:

• 11+ years of hands-on DV experience in System Verilog/UVM.
• Must be able to own and drive the verification of a block / subsystem or a SOC.
• Should have a track record of leading a team of engineers.
• Extensive experience in IP/sub-system and/or SoC level verification based on SV/UVM.
• Experience in Test plan and Testbench development,
• Execution of test plan using high quality constrained random UVM tests to hit coverage goals on time.
• Should be good with debugging and exposed to all aspects of verification flow including Gatesims
• Must have extensive experience in verification of one or more of the following:
  • PCI Express or UCIe, CXL or NVMe
  • AXI, ACE or CHI
  • Ethernet, RoCE or RDMA
  • DDR or LPDDR or HBM
  • ARM or RISC-V CPU based subsystem or SOC level verification using C/Assembly languages
  • Power Aware Simulations using UPF
• Experience in using one or more of EDA tools such as VCS, Verdi, Cadence Xcelium, Simvision, Jasper.
• Experience in using one or more of revision control systems such as: Git, Perforce, Clearcase.
• Experience in SVA and formal verification is desirable (not a must)
• Script development using Python, Perl or TCL is desirable (not a must)

Skills

• Systemverilog
• UVM
• SoC
• ip verification
• PCIE
• UCIE
• CXL
• NVMe
• CHI
• Ethernet
• ROCE
• RDMA
• DDR7
• LPDDR5
• HBM
• ARM
• RISC-V
• C
• Assembly
• power aware
• Jasper

Contact

Uday

[e-mail]

Mulya Technologies

"Mining the Knowledge Community"