Digital Hardware Design Verification Engineer

Pqangels Technologies; Hyderabad, Bengaluru; On-site; INR 1,200,000 - 1,800,000; Full time

Job summary

PQAngels Technologies is seeking an Experienced Design Verification Engineer in Hyderabad, India. You will work on SoC and IP-level verification, developing robust UVM environments and comprehensive verification plans.

The role requires strong SystemVerilog, UVM, and SVA skills, plus hands-on experience with functional coverage and protocol verification across AMBA/AXI/APB/AHB/PCIe/DDR/USB/Ethernet. Collaboration with RTL, PD, and customers is essential.

Qualifications

• Strong hands-on experience with SystemVerilog and UVM.
• Proficient in SystemVerilog Assertions (SVA).
• Experience with Functional Coverage and achieving coverage closure.
• Hands-on experience in protocol verification (AMBA/AXI/APB/AHB/PCIe/DDR/USB/Ethernet).
• Programming/scripting in Python and/or TCL.

Responsibilities

• Develop verification plans and strategies for SoC and IP-level projects.
• Build reusable UVM-based verification environments and testbenches.
• Create test scenarios and verification components; execute regressions.
• Perform functional and code coverage analysis; drive coverage closure.
• Debug and resolve verification issues; perform root-cause analysis.
• Conduct protocol-level verification and validation; sign-off activities.
• Collaborate with RTL, PD, and cross-functional teams; engage with customers.

Skills

SystemVerilog

UVM

SystemVerilog Assertions

Functional Coverage

Protocol verification (AMBA/AXI/APB/AH

Python/TCL

Job description

About Company :

PQAngels Technologies is a Product Engineering company focused on the complete Silicon-to-Software stack. Founded by Experienced Engineers, we help customers accelerate innovation across Semiconductor, ASIC, VLSI, Embedded, and Product Engineering domains.

Role Overview :

We are looking for Experienced Design Verification Engineers with strong expertise in SystemVerilog and UVM to work on SoC and IP-level verification projects. The ideal candidate should have hands‑on experience in developing robust verification environments, functional coverage closure, protocol verification, debugging, and verification sign-off activities.

Key Responsibilities :

• Develop comprehensive verification plans and strategies.
• Design and develop reusable UVM-based verification environments.
• Develop testbenches, test scenarios, and verification components.
• Perform functional and code coverage analysis and drive coverage closure.
• Develop and debug SystemVerilog Assertions (SVA).
• Execute regressions and analyze failures.
• Perform root-cause analysis and resolve verification issues.
• Conduct protocol-level verification and validation.
• Collaborate closely with RTL, Physical Design (PD), and other cross‑functional teams.
• Interact with customers and participate in technical discussions.
• Prepare and maintain verification documentation.
• Support verification sign-off activities and project milestones.

Mandatory Technical Skills :

• Strong hands‑on experience in SystemVerilog.
• Strong expertise in UVM.
• Good knowledge of SystemVerilog Assertions (SVA).
• Experience with Functional Coverage and coverage closure.
• Experience in protocol verification, preferably with one or more of the following:
  • AMBA
  • AXI
  • APB
  • AHB
  • PCIe
  • DDR
  • USB
  • Ethernet
• Programming/scripting experience in Python and/or TCL.