ASIC Design Verification

L&T Technology Services; Bengaluru; On-site; INR 1,500,000 - 2,100,000; Full time

Job summary

L&T Technology Services Bengaluru seeks DV engineers to define and implement verification plans and build test benches for IP/sub-stem/SoC verification. The role emphasizes developing functional tests per the plan and driving verification closure with metrics and coverage.

You will debug and root-cause functional failures in collaboration with the Design team, ensuring robust verification of ARM/RISC-V cores and IPs.

Qualifications

• Bachelor’s or Masters degree in Computer Science, Electronics Engineering or equivalent practical experience.
• 8/10+ hands-on experience in StemVerilog/UVM methodology and/or C/C++ based verification
• 8/ 10+ experience in IP/sub-stem and/or SoC level verification based on StemVerilog UVM/OVM based methodologies
• Experience in development of UVM based verification environments from scratch
• Experience in architecting and implementing Design Verification infrastructure and executing the full verification cycle
• Experience with verification of ARM/RISC-V based CPU sub-stems or SoCs
• Experience with IP or integration verification along with expertise of protocols like AMBA, PCIe, DDR, USB, Ethernet
• Experience in E tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments
• Experience with revision control stems like Mercurial(Hg), Git or SVN

Responsibilities

• Define and implement DV plans and test benches.
• Develop functional tests based on verification test plan.
• Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage.
• Debug, root-cause and resolve functional failures in the design, partnering with the Design team

Skills

StemVerilog/UVM

C/C++ verification

IP/Sub-SoC verification

UVM test environments

Verification infrastructure

ARM/RISC-V verification

Protocols AMBA/PCIe/DDR/USB/Ethernet

Python scripting

Mercurial/Git/SVN

Education

Bachelor’s or Master’s in CS/Electronics

Tools

Mercurial

Git

SVN

Job description

Job Description DV Positions:

Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-stem/SoC level verification

Develop functional tests based on verification test plan

Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage

Debug, root-cause and resolve functional failures in the design, partnering with the Design team

Qualifications and Skills for DV Positions:

Bachelor's or Masters degree in Computer Science, Electronics Engineering or equivalent practical experience

8/10+ of hands-on experience in StemVerilog/UVM methodology and/or C/C++ based verification

8/ 10+ experience in IP/sub-stem and/or SoC level verification based on StemVerilog UVM/OVM based methodologies

Experience in development of UVM based verification environments from scratch

Experience in architecting and implementing Design Verification infrastructure and executing the full verification cycle

Experience with verification of ARM/RISC-V based CPU sub-stems or SoCs

Experience with IP or integration verification along with expertise of protocols like AMBA, PCIe, DDR, USB, Ethernet

Experience in E tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments

Experience with revision control stems like Mercurial(Hg), Git or SVN