DFT Engineer - Hardware

NVIDIA; Bengaluru; Hybrid; INR 800,000 - 1,200,000; Full time

Job summary

NVIDIA is seeking a DFT Engineer in Bengaluru, India, to lead end-to-end DFT processes from RTL design to silicon validation. The ideal candidate will have a BSEE or MSEE and 2+ years of experience, focusing on DFT architecture, verification, and working with multi-functional teams.

The role involves responsibilities such as verification of DFT features, deploying methodologies for next-generation products, and is hybrid with potential travel. Strong knowledge in static timing analysis and scripting is also required.

Qualifications

• 2+ years of experience in DFT.
• Familiar with RTL and Gates verification and simulation.
• Strong analytical and problem-solving skills.

Responsibilities

• Responsible for end-to-end DFT from RTL design to Gate level scan insertion.
• Verification and silicon bringup of Scan ATPG and other DFT features.
• Develop and deploy DFT methodologies for next generation products.

Skills

Static Timing Analysis

ASIC/Logic Design Flow

DFT knowledge in Scan ATPG

Digital Logic Design

Scripting knowledge (Perl/Python)

Education

BSEE or MSEE

Tools

JTAG

BIST architecture

Job description

NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. Make the choice to join us today. NVIDIA is an equal opportunity employer. Design-for-Test Engineering at NVIDIA works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry's most complex semiconductor chips. We are looking for a DFT Engineer.

What you\'ll be doing:

• As a member in our team, you will be responsible for end-to-end DFT from RTL design to Gate level scan insertion to Verification (including JTAG, boundary scan, security mechanisms, and test clocking—across various test modes, including multiple ATPG configurations) to silicon bring-up.

• Your responsibility will also include verification and silicon bringup of Scan ATPG and other DFT features.

• In addition, you will help develop and deploy DFT methodologies for our next generation products.

• Be apart of innovation to strive improve the quality of DFT methods.

• You will also need to work with multi-functional teams to incorporate DFT features into the chip.

• Occasional travel and also some late hours online meetings involved during critical milestones.

What we need to see:

• BSEE or MSEE from reputed institutions or equivalent experience with 2+ years of experience

• You should be well versed with static timing Analysis, ECO, ASIC/Logic Design Flow, HDL and Digital logic design.

• Experience in RTL and Gates verification and simulation.

• You need to be familiar with BIST architecture and JTAG/IEEE1149.1/IEEE1500.

• Strong DFT knowledge in Scan ATPG, compression techniques and memory test.

• Strong analytical and problem solving skills with good scripting knowledge (either Perl / Python)

#LI-Hybrid