DFT Engineer - Hardware

NVIDIA Gruppe; Bengaluru; On-site; INR 800,000 - 1,200,000; Full time

Job summary

NVIDIA Gruppe in Bengaluru is looking for a DFT Engineer responsible for end-to-end design for test (DFT) from RTL design to silicon bring-up. The ideal candidate will need to work with multi-functional teams and travel occasionally during critical milestones.

The role requires a BSEE or MSEE and strong analytical skills with experience in DFT methodologies, static timing analysis, and logic design. Join us to be a part of innovation in next-generation products.

Qualifications

• 2+ years of experience in the relevant field.
• Well-versed with static timing analysis and digital logic design.
• Experience in verification and simulation of RTL and gates.

Responsibilities

• Responsible for end-to-end DFT from RTL design to silicon bring-up.
• Verification of Scan ATPG and other DFT features.
• Develop and deploy DFT methodologies for next-gen products.

Skills

Static timing analysis

ECO

ASIC/Logic Design Flow

HDL

Digital logic design

BIST architecture

JTAG/IEEE1149.1/IEEE1500

DFT knowledge

Scan ATPG

Scripting (Perl/Python)

Education

BSEE or MSEE from reputed institutions or equivalent experience

Job description

NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. Make the choice to join us today. NVIDIA is an equal opportunity employer.

What you'll be doing

• As a member in our team, you will be responsible for end-to-end DFT from RTL design to Gate level scan insertion to verification (including JTAG, boundary scan, security mechanisms, and test clocking—across various test modes, including multiple ATPG configurations) to silicon bring‑up.
• Your responsibility will also include verification and silicon bring‑up of Scan ATPG and other DFT features.
• In addition, you will help develop and deploy DFT methodologies for our next‑generation products.
• Be apart of innovation to strive improve the quality of DFT methods.
• You will also need to work with multi‑functional teams to incorporate DFT features into the chip.
• Occasional travel and also some late hours online meetings involved during critical milestones.

What we need to see

• BSEE or MSEE from reputed institutions or equivalent experience with 2+ years of experience.
• You should be well versed with static timing analysis, ECO, ASIC/Logic Design Flow, HDL and digital logic design.
• Experience in RTL and gates verification and simulation.
• You need to be familiar with BIST architecture and JTAG/IEEE1149.1/IEEE1500.
• Strong DFT knowledge in Scan ATPG, compression techniques and memory test.
• Strong analytical and problem‑solving skills with good scripting knowledge (either Perl / Python).