DFT Engineer

NVIDIA; Hyderabad; On-site; INR 1,000,000 - 1,500,000; Full time

Job summary

NVIDIA is hiring a Design-for-Test Engineer in Hyderabad. You will be responsible for the design and implementation of advanced test access mechanisms and DFT methodologies for next-generation products. Ideal candidates have a BSEE/MSEE and 2+ years of experience in design for testability, with strong analytical skills and proficiency in scripting languages. Join us to be part of a diverse, collaborative environment focused on innovation.

Qualifications

• 2+ years of experience in design for testability (DFT).
• Proficient in ASIC/logic design flow and HDL.
• Familiarity with Scan ATPG and compression techniques.

Responsibilities

• Design and implement state-of-the-art test access mechanisms.
• Verify and conduct silicon bring-up of DFT features.
• Develop and deploy methodologies for next-generation products.

Skills

Static timing analysis

Problem-solving skills

Scripting languages

DFT knowledge

Memory test techniques

Education

BSEE or MSEE

Tools

JTAG/IEEE1149.1

BIST architecture

Job description

NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life’s work, to amplify human creativity and intelligence. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world!

Design-for-Test Engineering at NVIDIA works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry's most complex semiconductor chips.

What You’ll Be Doing

• As a member of our team, you will be responsible for the design and implementation of state-of-the‑art designs in test access mechanisms, memory BIST and scan compression.
• Your responsibility will also include verification and silicon bring‑up of Scan ATPG and other DFT features.
• In addition, you will help develop and deploy DFT methodologies for our next‑generation products.
• Be part of innovation to strive to improve the quality of DFT methods.
• You will also need to work with multi‑functional teams to incorporate DFT features into the chip.
• Occasional travel and some late‑hours online meetings during critical milestones.

What We Need To See

• BSEE or MSEE from a reputed institution or equivalent experience.
• 2+ years of experience, preferably in design for testability (DFT).
• You should be well‑versed with static timing analysis, ECO, ASIC/logic design flow, HDL and digital logic design.
• Experience in RTL and gates verification and simulation.
• You need to be familiar with BIST architecture and JTAG/IEEE1149.1/IEEE1500.
• Strong DFT knowledge in Scan ATPG, compression techniques and memory test.
• Strong analytical and problem‑solving skills.
• Expert coding skills in industry‑standard scripting languages.
• Extraordinary written and oral communication skills with the curiosity to work on rare challenges.

NVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most brilliant and talented people on the planet working for us. If you're creative and autonomous, we want to hear from you! NVIDIA is committed to fostering a diverse work environment and proud to be an equal‑opportunity employer.