DFT Engineer - Hardware

NVIDIA Corporation; Bengaluru; On-site; INR 800,000 - 1,200,000; Full time

Job summary

NVIDIA Corporation is seeking a DFT Engineer in Bengaluru, India. As a key member of the Design-for-Test Engineering team, you will oversee the complete DFT process from RTL design to silicon verification and methodology deployment.

The ideal candidate should possess a BSEE or MSEE, accompanied by over 2 years of experience in DFT engineering, ASIC design flow, and scripting skills in Perl or Python. Join us in driving innovations in the semiconductor industry.

Qualifications

• A minimum of 2 years of experience in DFT engineering.
• Proficiency in RTL design and Gate level verification.
• Familiarity with JTAG protocols and testing mechanisms.

Responsibilities

• Responsible for end-to-end DFT from RTL to silicon.
• Verify DFT methodologies and features for next-generation products.
• Collaborate with multi-functional teams to implement DFT features.

Skills

Static Timing Analysis

ECO

ASIC/Logic Design Flow

HDL

Digital Logic Design

BIST Architecture

JTAG/IEEE1149.1/IEEE1500

Scan ATPG

Compression Techniques

Memory Test

Scripting (Perl/Python)

Education

BSEE or MSEE

Job description

## DFT Engineer - HardwareApplylocations: India, Bengalurutime type: Full timeposted on: Posted Todayjob requisition id: JR2018054NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. Make the choice to join us today. NVIDIA is an equal opportunity employer. Design-for-Test Engineering at NVIDIA works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry's most complex semiconductor chips. We are looking for a DFT Engineer.**What you'll be doing:*** As a member in our team, you will be responsible for end-to-end DFT from RTL design to Gate level scan insertion to Verification (including JTAG, boundary scan, security mechanisms, and test clocking—across various test modes, including multiple ATPG configurations) to silicon bring-up.* Your responsibility will also include verification and silicon bringup of Scan ATPG and other DFT features.* In addition, you will help develop and deploy DFT methodologies for our next generation products.* Be apart of innovation to strive improve the quality of DFT methods.* You will also need to work with multi-functional teams to incorporate DFT features into the chip.* Occasional travel and also some late hours online meetings involved during critical milestones.**What we need to see:*** BSEE or MSEE from reputed institutions or equivalent experience with 2+ years of experience* You should be well versed with static timing Analysis, ECO, ASIC/Logic Design Flow, HDL and Digital logic design.* Experience in RTL and Gates verification and simulation.* You need to be familiar with BIST architecture and JTAG/IEEE1149.1/IEEE1500.* Strong DFT knowledge in Scan ATPG, compression techniques and memory test.* Strong analytical and problem solving skills with good scripting knowledge (either Perl / Python)