Senior Design Verification Professionals_Eximietas Design

Eximietas Design; Hyderabad; On-site; INR 11,472,000 - 17,208,000; Full time

Job summary

Eximietas Design is seeking an experienced SoC Design Verification lead to drive verification strategies for complex projects in the USA, with teams across architects, designers, and pre/post-silicon verification groups.

You will own verification plans, develop test benches, implement coverage, and mentor junior engineers while ensuring on-time sign-off and adherence to quality standards.

Qualifications

• 4+ years hands-on experience in SoC Design Verification.
• Expertise in high-speed SoCs and protocols including I2C/I3C, SPI, UART, GPIO, QSPI, PCIe, Ethernet, CXL, MIPI, DDR, HBMs.
• Proficiency in SystemVerilog for verification with assertions and coverage.
• Experience with gate-level simulations and power-aware verification using Xprop and UPF.
• Strong hands-on experience with VCS and Xsim from Synopsys and Cadence.
• Mentorship experience and ability to lead verification teams.
• Cross-functional collaboration ensuring verification sign-off.

Responsibilities

• Lead SoC Design Verification efforts and verification plans.
• Develop verification strategies with testbenches and coverage analysis.
• Conduct gate-level simulations and power-aware verification.
• Collaborate with architects, designers, and pre/post-silicon teams.
• Implement SystemVerilog assertions and functional coverage.
• Mentor junior verification engineers and lead the team.
• Ensure verification sign-off criteria with documentation.
• Adhere to quality standards and best test practices.

Skills

SoC Verification

SystemVerilog

Testbenches

Assertions

Functional Coverage

Gate-level Sim

Power-aware

VCS

Xsim

VIP Integration

Mentorship

Tools

Synopsys VCS

Cadence Xsim

UPF

Xprop

Verification IP

Synopsys Cadence

Job description

Experience: 4 to 20+ Years.

Locations:

• San Jose (Bay Area), USA
• Austin, USA
• Eligibility (USA): U.S. Permanent Residents (Green Card holders).

Job Description:

• Lead SoC Design Verification efforts for complex projects, ensuring successful execution of verification plans.
• Develop and implement comprehensive verification strategies, including test plans, testbenches, and coverage analysis, for both high-speed and low-speed peripherals (e.g., I2C, SPI, UART, GPIO, QSPI) as well as high-speed protocols (e.g., PCIe, Ethernet, CXL, MIPI, DDR, HBM).
• Conduct Gate-level simulations and power-aware verification using tools like Xprop and UPF.
• Collaborate closely with cross-functional teams, including architects, designers, and pre/post-silicon verification teams, to ensure alignment and seamless integration of verification efforts.
• Analyze and implement System Verilog assertions and functional coverage (code, toggle, functional) to ensure thorough verification of design functionality.
• Provide mentorship and technical guidance to junior verification engineers, helping to elevate team performance.
• Lead and manage a dynamic team of verification engineers, fostering a collaborative and innovative work environment.
• Ensure that all verification signoff criteria are met, with clear and comprehensive documentation.
• Demonstrate strong dedication, work ethic, and commitment to meeting project goals and deadlines.
• Uphold quality standards and implement best test practices, contributing to continuous improvements in verification methodologies.
• Work with verification tools from Synopsys and Cadence, including VCS and Xsim.
• Integrate third-party VIPs (Verification IP) from Synopsys and Cadence to enhance verification coverage.

Qualifications:

• 4+ years of hands-on experience in SoC Design Verification.
• Expertise in verification of high-speed SoCs and various protocols, including I2C/I3C, SPI, UART, GPIO, QSPI, PCIe, Ethernet, CXL, MIPI, DDR, and HBM.
• Proficiency in System Verilog for verification, including assertions and coverage.
• Experience with gate-level simulations and power-aware verification using Xprop and UPF.
• Strong hands-on experience with VCS and Xsim from Synopsys and Cadence.
• Mentorship experience, providing guidance to junior engineers and managing verification teams.
• Demonstrated ability to work with cross-functional teams, ensuring effective collaboration and verification signoff.
• Strong understanding of verification methodologies and ability to contribute to their continuous improvement.