Design Verification Engineer_Eximietas Design

Eximietas Design

Bengaluru

On-site

INR 10,000,000 - 20,000,000

Full time

14 days+

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Job summary

Eximietas Design is seeking an experienced professional in ASIC / SoC Design Verification to work on cutting-edge semiconductor technologies. The ideal candidate should have substantial experience in verification, including SystemVerilog/UVM coding and understanding of ASIC design concepts. Responsibilities include collaborating with engineering teams, engaging in innovative projects, and contributing to career growth. The position is based in Bengaluru, Karnataka, India.

Qualifications

  • 4–25 years of ASIC / SoC Design Verification experience.
  • Strong understanding of ASIC design concepts and verification flow.
  • Good understanding of coverage analysis and debug missing scenarios.

Responsibilities

  • Work on cutting-edge SoC and semiconductor technologies.
  • Engage in collaborative and innovation-driven engineering culture.
  • Focus on career growth and technical leadership.

Skills

ASIC / SoC Design Verification
SystemVerilog / UVM coding
Execution in IP, Subsystem, and SoC level verification
Understanding of RAL methodology

Tools

VCS
Xcelium
Git
SVN
Perforce

Job description

Locations
  • San Jose (Bay Area), USA
  • Austin, USA
  • Eligibility (USA): U.S. Permanent Residents (Green Card holders).
Key Qualifications
  • 4–25 years of ASIC / SoC Design Verification experience
  • Strong understanding of ASIC design concepts and verification flow
  • Experience in IP, Subsystem, and SoC level verification
  • Strong SystemVerilog / UVM coding expertise
  • Good understanding of RAL methodology
Protocol Experience
  • Low-speed peripherals: I2C, SPI, QSPI, DMA, UART, GPIO, Interrupt Controllers
  • High-speed protocols: PCIe, CXL, Ethernet, USB
  • Memory protocols: DDR, LPDDR, HBM
Tools & Methodologies
  • Simulation tools: VCS, Xcelium
  • Waveform analyzers & Third-party VIP integration
  • Version control: Git, SVN, Perforce
  • Experience with GLS and Power Aware Simulation (UPF)
  • Define verification strategy, test plans & coverage plans
  • Implement SystemVerilog assertions & functional coverage
  • Perform coverage analysis and debug missing scenarios
  • Collaborate with design, architecture, and pre/post-silicon teams
  • Work closely with customer leads and ensure verification sign-off
Responsibilities
  • Work on cutting-edge SoC and semiconductor technologies
  • Engage in collaborative and innovation-driven engineering culture
  • Focus on career growth and technical leadership
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