Sr. Manager Verification

Semtech; Hyderabad; Sur place; INR 1 200 000 - 1 800 000; Plein temps

Résumé du poste

Semtech is seeking a Verification Engineer in Hyderabad to lead a team of verification engineers across multiple projects, overseeing deliverables and quality. The role requires extensive experience in integrated circuit design verification, including managing complex digital and mixed-signal designs. Candidates must have strong leadership skills and proficiency in System Verilog and UVM.

The ideal candidate will have a B.S. or M.S. in Electrical or Computer Engineering and proven success in leading technical teams.

Qualifications

• 8+ years of industry experience in integrated circuit design verification.
• 3+ years in a technical leadership or management role.
• Proven track record of successful tape-outs for complex designs.

Responsabilités

• Lead, supervise, mentor, and develop a team of verification engineers.
• Track and report verification progress using metrics and coverage analysis.
• Manage design and implementation of complex testbenches using System Verilog.

Connaissances

Integrated circuit design verification

System Verilog

UVM implementation

Digital hardware knowledge

Analytical skills

Communication skills

Formation

B.S. or M.S. in Electrical or Computer Engineering

Outils

EDA verification tools (Synopsys, Cadence, Siemens)

Scripting languages (Python, Perl)

Description du poste

Responsibilities

• Lead, supervise, mentor, and develop a team of verification engineers across multiple projects. Manage verification team deliverables, quality, schedules, and resource allocation for concurrent projects. (20%)
• Track & report verification progress using quantitative metrics and coverage analysis. Identify and mitigate verification risks early. Report to remote verification & design teams. Coordinate with project management and cross‑functional teams. (20%)
• Drive definition and implementation of comprehensive verification plans and test strategies for digital/mixed‑signal integrated circuit designs. Work closely with design teams to understand micro‑architecture and functional specifications. Direct detailed test plans, coverage models, and verification environments. Drive coverage closure including functional, code, and assertion‑based coverage. Generate technical documentation and drive verification reviews. (20%)
• Manage design and implementation of complex testbenches using System Verilog and UVM methodology. Lead block and chip‑level register‑transfer level (RTL), gate‑level and analog/mixed‑signal (AMS) verification. Develop directed test cases, constrained‑random verification environments and reusable verification components. Improve verification scalability and portability from project to project by environment enhancement and tools automation. Establish and manage continuous integration, regression testing, scoreboards, monitors, and checkers. (20%)
• Interface with system, digital hardware, embedded firmware, analog and cross‑functional teams. (10%)
• Drive adoption of advanced verification methodologies, best practices and tool evaluation. (5%)
• Technical support to silicon lab evaluation, test, product and application engineers. (5%)

Minimum Qualifications

• 8+ years of industry experience in integrated circuit design verification (DV)
• 3+ years in a technical leadership or management role
• B.S. or M.S. in Electrical or Computer Engineering
• Proven track record of successful tape‑outs for complex digital or mixed‑signal designs
• Demonstration of ability to lead technical teams and drive high‑quality & timely results
• Experience managing concurrent projects, competing priorities and sub‑teams
• Strong analytical, synthesis and problem solving skills
• In‑depth knowledge and experience in digital IC verification for mixed‑signal ICs with MCU based hardware systems (ARM, RISC‑V, PIC, STM32) with memories, custom digital micro‑architecture, interfaces, dedicated hardware peripherals, embedded signal processing, external IPs, and analog peripherals.
• Proficiency in System Verilog as High‑level Verification Language and UVM implementation, Verilog/VHDL, scripting languages (Python, Perl), debugging capabilities, and industry leading EDA verification tools (Synopsys, Cadence, Siemens)
• Experience with standard hardware protocols (I2C, I3C, SPI, MIPI)
• Independent, self‑motivated, rigorous, innovating, team player and able to follow through
• Excellent verbal and written communication skills

Desired Qualifications

• Knowledge of system‑level aspects: signal processing, mixed‑signal, digital hardware, embedded firmware, analog, modelling, test and application
• Experience with analog block behavioural modelling with SV RNM/Verilog/VHDL
• Experience with consumer and/or ITA market circuit developments