Senior Design Verification Professionals_Eximietas Design

Eximietas Design; Bengaluru; On-site; INR 11,494,252 - 14,367,816; Full time

Job summary

Eximietas Design is seeking Senior Design Verification Professionals to lead verification efforts for complex SoC projects. Responsibilities include developing strategies, conducting simulations, and mentoring junior engineers. Ideal candidates have a minimum of 4 years of hands-on experience in verification of high-speed protocols and System Verilog proficiency. Join a dedicated team focused on quality and innovation in a highly collaborative environment. Locations include San Jose and Austin, USA.

Qualifications

• Minimum 4+ years of hands-on experience in SoC Design Verification.
• Expertise in verification of high-speed SoCs and various protocols.
• Proficiency in System Verilog for verification.

Responsibilities

• Lead SoC Design Verification efforts for complex projects.
• Develop comprehensive verification strategies and test plans.
• Provide mentorship and technical guidance to junior engineers.

Skills

SoC Design Verification

High-speed protocols (e.g., PCIe, Ethernet)

System Verilog

Gate-level simulations

Mentorship

Collaboration

Tools

VCS

Xsim

Xprop

UPF

Job description

We are Hiring: Senior Design Verification Professionals.

Experience:

• 4 to 20+ Years

Locations:

• San Jose (Bay Area), USA
• Austin, USA
• Eligibility (USA): U.S. Permanent Residents (Green Card holders).

Job Responsibilities

• Lead SoC Design Verification efforts for complex projects, ensuring successful execution of verification plans.
• Develop and implement comprehensive verification strategies, including test plans, testbenches, and coverage analysis, for both high-speed and low-speed peripherals (e.g., I2C, SPI, UART, GPIO, QSPI) as well as high-speed protocols (e.g., PCIe, Ethernet, CXL, MIPI, DDR, HBM).
• Conduct gate-level simulations and power-aware verification using tools like Xprop and UPF.
• Collaborate closely with cross‑functional teams, including architects, designers, and pre/post‑silicon verification teams, to ensure alignment and seamless integration of verification efforts.
• Analyze and implement System Verilog assertions and functional coverage (code, toggle, functional) to ensure thorough verification of design functionality.
• Provide mentorship and technical guidance to junior verification engineers, helping to elevate team performance.
• Lead and manage a dynamic team of verification engineers, fostering a collaborative and innovative work environment.
• Ensure that all verification signoff criteria are met, and sign off with clear and measurable outcomes.
• Demonstrate strong dedication, work ethic, and commitment to meeting project goals and deadlines.
• Uphold quality standards and implement best test practices, contributing to continuous improvements in verification methodologies.
• Work with verification tools from Synopsys and Cadence, including VCS and Xsim.
• Integrate third‑party VIPs (Verification IP) from Synopsys and Cadence to enhance verification coverage.

Qualifications

• Minimum 4+ years of hands‑on experience in SoC Design Verification.
• Expertise in verification of high‑speed SoCs and various protocols, including I2C/I3C, SPI, UART, GPIO, QSPI, PCIe, Ethernet, CXL, MIPI, DDR, and HBM.
• Proficiency in System Verilog for verification, including assertions and coverage.
• Experience with gate‑level simulations and power‑aware verification using Xprop and UPF.
• Strong hands‑on experience with VCS and Xsim from Synopsys.
• Mentorship experience, providing guidance to junior engineers.
• Demonstrated ability to work with cross‑functional teams, ensuring effective collaboration and verification signoff.
• Strong understanding of verification methodologies and ability to contribute to their continuous improvement.

Preferred Qualifications

• Experience in third‑party VIP integration (Synopsys/Cadence).
• Prior experience in leading large verification teams and projects.
• Familiarity with pre/post‑silicon verification processes.