AMS Verification with Memory

leadIC Design Pvt Ltd; Hyderabad; On-site; INR 600,000 - 1,200,000; Full time

Job summary

A leading design company in Hyderabad is seeking an experienced professional to take ownership of verification and analysis of complex full-chip designs. Responsibilities include providing support through simulation and debugging, developing test cases, and collaborating internationally on verification methodologies. Candidates should have a good understanding of CMOS designs and familiarity with tools like SystemVerilog. An analytical mindset is preferred, along with experience in memory technologies.

Qualifications

• Basic understanding of CMOS and gate level circuit designs.
• Familiarity with SPICE.
• Experience in DRAM, SRAM or other memory-related fields.

Responsibilities

• Provide verification support to design projects by simulating and analyzing designs.
• Develop Test cases/Stimulus for coverage improvement.
• Collaborate with international colleagues on verification flows.

Skills

CMOS understanding

Gate level circuit design

SPICE familiarity

Verilog simulations

Good communication

Tools

SystemVerilog

UVM Test Bench

Job description

**Unique Opportunities** Complete ownership of verification and end to end analysis of complex full-chip gate level custom designs with advanced low power and power management technologies spread across multiple categories such as DDR4, LPDDR4, DDR5, and LPDDR5 that are capable of operating at high speeds of up to 6400MT/s. Collaborate closely with design and verification team members spread across the globe, many of whom have decades of experience in memory design. Work on cross functional tasks that can widen your skill set.**Responsibilities** Provide verification support to design projects by simulating, analyzing and debugging pre-silicon full chip designs. Develop Test cases/Stimulus to increase the functional coverage for all DRAM and emerging memory architectures and features. Develop and maintain test benches and test vectors using simulation tools and run regressions for coverage analysis and improvements. Co-work with international colleagues on developing new verification flows to take on the challenges in DRAM and emerging memory design. Participate in developing verification methodology and verification environments for advanced DRAM and emerging memory products.**Core Requirements** Basic understanding of CMOS and gate level circuit designs Familiarity with SPICE Familiarity with Verilog simulations Good communication skills and ability to work well in a team**Preferred Qualities** Analytical capability for complex gate level circuit designs Experience in SystemVerilog, PLI coding Experience in UVM Test Bench Experience in DRAM, SRAM or other memory related fields Experience in AMS verification and co-sim**Job Location:** Hyderabad