Lead Design Verification Engineer

LeadSoc Technologies Pvt Ltd; Bengaluru; On-site; INR 2,500,000 - 5,000,000; Full time

Job summary

LeadSoc Technologies Pvt Ltd in Bengaluru is seeking a senior Design Verification Engineer to own verification for Ethernet/SerDes IPs and drive UVM-based validation. You will create testbenches, drive coverage, and work with RTL, firmware, PHY, and systems teams to achieve sign-off on high-speed interfaces.

The role requires 6–12 years of hands-on experience with SystemVerilog/UVM/SVA and strong Ethernet protocol verification skills, including link training and data integrity checks.

Qualifications

• 6–12 years of hands‑on Design Verification experience.
• Strong SystemVerilog, UVM, SVA, and verification methodology expertise.
• Hands‑on experience in Ethernet protocol & compliance verification.
• Strong experience in SerDes/controller validation and high‑speed interface verification.
• Proven expertise in UVM environment development and reusable verification infrastructure.
• Strong understanding of Ethernet MAC/PCS/PHY, link protocols, packet processing, and error handling.

Responsibilities

• Own verification strategy, planning, execution, and signoff for Ethernet/SerDes/controller IPs.
• Drive Ethernet protocol and compliance verification across functional, corner-case, and error scenarios.
• Perform SerDes and Ethernet controller validation, including link training, data integrity, error handling, and interoperability.
• Develop UVM agents, sequences, scoreboards, monitors, assertions, coverage models, and protocol checkers.
• Drive constrained-random, coverage-driven, assertion-based, and regression verification.
• Debug complex RTL/protocol issues using simulation, waveform, and regression analysis.
• Collaborate with RTL, architecture, firmware, PHY, and system teams to achieve verification closure.

Skills

Design Verification

SystemVerilog

UVM

SVA

Ethernet protocol verification

SerDes validation

Ethernet controller validation

UVM environment development

Ethernet MAC/PCS/PHY

Python/Perl/Tcl scripting

Tools

UVM tooling

Job description

We are looking for a strong Lead Design Verification Engineer with deep expertise in Ethernet protocol & compliance verification, SerDes/controller validation, and UVM environment development to drive verification of complex networking and high-speed interface IPs.

Key Responsibilities

• Own verification strategy, planning, execution, and signoff for Ethernet/SerDes/controller IPs.
• Drive Ethernet protocol and compliance verification across functional, corner-case, and error scenarios.
• Perform SerDes and Ethernet controller validation, including link training, data integrity, error handling, and interoperability.
• Develop UVM agents, sequences, scoreboards, monitors, assertions, coverage models, and protocol checkers.
• Drive constrained-random, coverage-driven, assertion-based, and regression verification.
• Debug complex RTL/protocol issues using simulation, waveform, and regression analysis.
• Collaborate with RTL, architecture, firmware, PHY, and system teams to achieve verification closure.

Required Skills

• 6–12 years of hands‑on Design Verification experience.
• Strong SystemVerilog, UVM, SVA, and verification methodology expertise.
• Hands‑on experience in Ethernet protocol & compliance verification.
• Strong experience in SerDes/controller validation and high‑speed interface verification.
• Proven expertise in UVM environment development and reusable verification infrastructure.
• Strong understanding of Ethernet MAC/PCS/PHY, link protocols, packet processing, and error handling.
• Experience with functional/coverage closure and complex protocol debug.
• Strong scripting skills in Python/Perl/Tcl are preferred.

Good to Have

• Experience with 10G/25G/50G/100G/200G/400G Ethernet.
• Exposure to Ethernet VIP, compliance testing, SerDes PHY, PCIe/CXL, or high‑speed interconnects.
• Experience leading verification teams/projects and driving end‑to‑end verification signoff.