Functional Verification Engineer

ACL Digital; Bengaluru; On-site; INR 1,200,000 - 2,400,000; Full time

Job summary

ACL Digital in Bangalore seeks a skilled Functional Verification Engineer to join our IP/SoC verification team. You will verify complex digital designs using industry-standard methodologies to ensure functional correctness and high-quality silicon delivery.

You will develop test plans and build testbenches with SystemVerilog/UVM, create constrained-random test cases, and perform coverage analysis to close gaps. Collaboration with design teams and thorough documentation are required.

Qualifications

• 4+ years of hands-on experience in functional verification of IP/SoC.
• Strong knowledge and working experience with SystemVerilog and UVM.
• Familiarity with RTL design (Verilog/VHDL).
• Experience in coverage-driven verification, assertions, and functional coverage closure.
• Proficient in using simulators like VCS, Questa, or Incisive.
• Good scripting skills in Perl, Python, or Shell for automation.
• Strong debugging skills using simulation waveform viewers.
• Good understanding of common protocols such as AXI, AHB, APB, PCIe, USB, etc.

Responsibilities

• Develop and execute verification test plans based on design specifications and architecture.
• Design and implement testbenches using SystemVerilog and UVM methodology.
• Create constrained-random and directed test cases.
• Build verification components (agents, monitors, scoreboards, checkers).
• Perform coverage analysis (code and functional) and close coverage gaps.
• Debug simulation failures and work closely with design and architecture teams.
• Conduct regressions and analyze results for functional and performance issues.
• Document test plans, verification environments, and test results.
• Participate in design and verification reviews.

Skills

SystemVerilog

UVM

RTL Design

Coverage-driven verification

Assertions

Perl

Python

Shell

Debugging

AXI/AMBA

VCS

Questa

Incisive

Education

B.E./B.Tech or M.E./M.Tech in ECE/EEE/Computer Engineering

Tools

VCS

Questa

Incisive

Job description

Job Title:

Functional Verification Engineer

Location:

Bangalore

Experience:

4+ Years

Job Type:

Full-time

Industry:

Semiconductor / VLSI / ASIC Design

Education:

B.E./B.Tech or M.E./M.Tech in ECE/EEE/Computer Engineering

Job Description:

We are seeking a skilled and detail-oriented Functional Verification Engineer to be part of our IP/SoC verification team. The candidate will be responsible for verifying complex digital designs using industry-standard methodologies to ensure functional correctness and high-quality silicon delivery.

Key Responsibilities:

• Develop and execute verification test plans based on design specifications and architecture.
• Design and implement testbenches using SystemVerilog and UVM methodology.
• Create constrained-random and directed test cases.
• Build verification components (agents, monitors, scoreboards, checkers).
• Perform coverage analysis (code and functional) and close coverage gaps.
• Debug simulation failures and work closely with design and architecture teams.
• Conduct regressions and analyze results for functional and performance issues.
• Document test plans, verification environments, and test results.
• Participate in design and verification reviews.

Required Skills:

• 4+ years of hands-on experience in functional verification of IP/SoC.
• Strong knowledge and working experience with SystemVerilog and UVM.
• Familiarity with RTL design (Verilog/VHDL).
• Experience in coverage-driven verification, assertions, and functional coverage closure.
• Proficient in using simulators like VCS, Questa, or Incisive.
• Good scripting skills in Perl, Python, or Shell for automation.
• Strong debugging skills using simulation waveform viewers.
• Good understanding of common protocols such as AXI, AHB, APB, PCIe, USB, etc