Senior Staff Engineer – CPU Verification

LeadSoc Technologies Pvt Ltd; Bengaluru; On-site; INR 4,200,000 - 6,400,000; Full time

Job summary

LeadSoc Technologies Pvt Ltd in Bengaluru is seeking a Senior Staff Engineer for CPU verification to own verification of complex CPU microarchitecture, drive testbench architecture, and deliver comprehensive functional verification for next-generation processor cores.

You will architect verification environments using SystemVerilog, UVM, and C/C++, verify OoO execution, branch prediction, and memory ordering, and lead coverage closure with cross-functional teams.

Qualifications

• 10–16 years in CPU/processor design verification.
• Expert in SystemVerilog, UVM, SVA.
• Experience with ARM/RISC-V/x86 ISA verification.
• Proficient in Python/C++/Perl for automation.

Responsibilities

• Architect and implement CPU verification environments using SystemVerilog, UVM, and C/C++.
• Verify CPU microarchitecture including OoO execution, branch prediction, memory ordering.
• Develop reference models, scoreboards, monitors, and coverage models.
• Drive constrained-random testing, regression and coverage closure, and signoff.

Skills

SystemVerilog

UVM

SVA

Constrained-random

Python

C/C++

Team leadership

Tools

Python

C/C++

Perl

Job description

Experience: 10–16 Years

Role Overview

We are seeking a Senior Staff Engineer – CPU Verification to own the verification of complex CPU microarchitecture, drive testbench architecture, and deliver comprehensive functional verification for next-generation processor cores.

Key Responsibilities

• Architect and implement CPU verification environments using SystemVerilog, UVM, and C/C++.


• Verify complex CPU microarchitecture, including:


• Out-of-Order (OoO) execution and instruction pipeline


• Branch prediction and speculative execution


• Register renaming, ROB, issue/dispatch, and execution units


• L1/L2 caches, TLB, MMU, and memory ordering


• Interrupts, exceptions, and privilege modes


• Develop advanced reference models, scoreboards, checkers, assertions, and functional coverage.


• Drive constrained-random testing, directed testing, architectural compliance, and corner-case validation.


• Debug complex RTL failures using waveform analysis, simulation, and emulation platforms.


• Own coverage closure, regression infrastructure, and verification signoff for critical CPU features.


• Collaborate with CPU RTL, microarchitecture, formal, performance, and post-silicon validation teams.

Core Technical Requirements

• 10–16 years of hands-on experience in CPU / Processor Design Verification.


• Expert-level proficiency in SystemVerilog, UVM, SVA, and constrained-random verification.


• Strong knowledge of CPU microarchitecture and instruction execution pipelines.


• Experience developing CPU verification components, including scoreboards, reference models, monitors, agents, and coverage models.


• Strong expertise in RTL simulation, debug, regression automation, and functional coverage closure.


• Experience with ARM, RISC-V, or x86 architecture and ISA-level verification.


• Proficiency in Python, C/C++, or Perl for verification automation.

Senior Staff Technical Ownership

• Own end-to-end verification architecture for critical CPU microarchitectural features.


• Define verification plans, identify architectural corner cases, and drive coverage closure.


• Develop reusable verification infrastructure and improve simulation and regression efficiency.


• Resolve complex design and verification challenges through technical innovation.


• Provide hands-on technical guidance to senior engineers and contribute to verification methodology.