Design Verification Engineer

Allegis Group; Bengaluru; On-site; INR 1,800,000 - 3,200,000; Full time

Job summary

Allegis Group in Bangalore is seeking a Design Verification Engineer with 3 to 5 years of experience to work on CPU architecture and verification of advanced processors. You will build UVM-based environments, develop test strategies, create directed and constrained-random tests, and collaborate with design teams to verify new CPU features and ensure coverage.

Candidates should have strong SystemVerilog, UVM, RTL debugging, and experience with x86/ARM/RISC-V architectures, Linux, and

Qualifications

• Bachelor's or Master's degree in Electrical/Electronics Engineering, Computer Engineering, Computer Science, or VLSI/architecture related fields.

Responsibilities

• Verify new CPU features and functionality
• Develop verification plans and test strategies
• Build and enhance UVM-based verification environments
• Create directed and constrained-random testcases
• Debug RTL, testbench, and regression failures
• Drive functional and code coverage closure
• Collaborate with design and architecture teams
• Mentor junior engineers and improve verification methodologies

Skills

System Verilog

UVM

ASIC / SoC Verification

Functional Verification

Testbench Development

Constrained Random Verification

SVA (System Verilog Assertions)

Coverage Development & Closure

RTL Debugging

Regression Debugging

Computer Architecture

CPU / Processor Verification

x86 / ARM / RISC-V Architecture

Python / C / C++

Linux / Unix Environment

Education

Electrical/Electronics Engineering

Computer Engineering

Computer Science

VLSI / Computer Architecture related fields

Job description

Hiring: Design Verification Engineer

Location: Bangalore
Experience: 3 to 5 Years

Are you passionate about CPU Architecture, Design Verification, and cutting-edge processor technology?

• System Verilog
• UVM
• ASIC / SoC Verification
• Functional Verification
• Testbench Development
• Constrained Random Verification
• SVA (System Verilog Assertions)
• Coverage Development & Closure
• RTL Debugging
• Regression Debugging
• Computer Architecture
• CPU / Processor Verification
• x86 / ARM / RISC-V Architecture
• Python / C / C++
• Linux / Unix Environment

Preferred Experience

• CPU Core Verification
• Microprocessor Verification
• Cache / Memory Subsystem Verification
• PCIe, UCIe, AXI, AHB, APB
• Superscalar & Out-of-Order Processor Architecture
• Verification Planning & Coverage Closure
• Working with Global Teams

Responsibilities

• Verify new CPU features and functionality
• Develop verification plans and test strategies
• Build and enhance UVM-based verification environments
• Create directed and constrained-random testcases
• Debug RTL, testbench, and regression failures
• Drive functional and code coverage closure
• Collaborate with design and architecture teams
• Mentor junior engineers and improve verification methodologies

Qualification

Bachelor's or Master's degree in:

• Electrical/Electronics Engineering
• Computer Engineering
• Computer Science
• VLSI / Computer Architecture related fields