Senior Design Verification Engineer

Weekday AI; Bengaluru; On-site; INR 1,500,000 - 1,800,000; Full time

Job summary

Weekday AI seeks a Senior Design Verification Engineer to lead CPU and SoC verification activities for advanced processor subsystems. You will design and implement UVM-based testbenches, develop coverage models, and verify multiple architectures including RISC-V, ARM, and x86.

The role requires strong SystemVerilog/UVM expertise, experience with AMBA protocols, and proficiency in EDA tools like VCS, Xcelium, and Questa. Expect collaboration across RTL, architecture, and firmware teams.

Qualifications

• Develop and execute CPU/SoC design verification strategies and test plans.
• Build, enhance, and maintain UVM-based verification environments using SystemVerilog.
• Develop reusable verification components, sequences, scoreboards, monitors, checkers, and coverage models.
• Verify CPU functionality across architectures such as RISC-V, ARM, x86, or custom cores.
• Develop test scenarios covering CPU pipeline execution, interrupts, exceptions, memory ordering, and architectural behaviour.
• Verify cache coherency and CPU/SoC subsystem interactions.
• Develop verification for AMBA protocols including AXI, AHB, ACE, and CHI.
• Run simulations using EDA tools like VCS, Xcelium, and Questa.
• Analyse simulation failures, debug complex issues, and identify root causes in RTL, testbench, or design behaviour.

Responsibilities

• Develop and execute comprehensive CPU and SoC design verification strategies.
• Build, enhance, and maintain UVM-based verification environments.
• Develop reusable verification components, sequences, monitors, scoreboards, and coverage models.
• Verify CPU functionality across architectures (RISC-V/ARM/x86/custom cores).
• Develop test scenarios covering CPU pipeline execution, interrupts, and memory ordering.

Skills

SystemVerilog

UVM

CPU verification

AMBA protocols

RISC-V

ARM

x86

Python scripting

C/C++

Debugging

Failure analysis

Team collaboration

Education

B.Tech/M.Tech in Electronics

Tools

Synopsys VCS

Cadence Xcelium

Siemens Questa

Palladium

Veloce

Zebu

Job description

This role is for one of the Weekly's clients

Salary range: Rs 1500000 - Rs 1800000 (ie INR 1515-14 LPA)

Experience: 5+ yrs

Location: Bengaluru, Hyderabad, Telangana, India

Job Type: Full-time

We are looking for an experienced Senior Design Verification Engineer to drive verification activities for CPU and SoC subsystems using industry-standard verification methodologies and tools. The role requires strong hands-on expertise in SystemVerilog, UVM, CPU verification, and ASIC/SoC design verification, with practical experience across modern processor architectures such as RISC-V, ARM, x86, or custom CPU cores.

The ideal candidate will have a strong understanding of CPU architecture, cache coherency, pipeline execution, AMBA protocols, and verification environments, along with the ability to develop robust testbenches, debug complex failures, and contribute to verification strategy and execution.

Requirements

KEY RESPONSIBILITIES

• Develop and execute comprehensive CPU and SoC design verification strategies and test plans.
• Build, enhance, and maintain UVM-based verification environments using SystemVerilog.
• Develop reusable verification components, sequences, scoreboards, monitors, checkers, and coverage models.
• Verify CPU functionality across architectures such as RISC-V, ARM, x86, or custom processor cores.
• Develop test scenarios covering CPU pipeline execution, interrupts, exceptions, memory ordering, and architectural behaviour.
• Verify cache coherency and CPU/SoC subsystem interactions.
• Develop and execute verification for AMBA protocols, including AXI, AHB, ACE, and CHI.
• Run simulations using industry-standard EDA tools such as VCS, Xcelium, and Questa.
• Analyse simulation failures, debug complex functional issues, and identify root causes in RTL, testbench, or design behaviour.
• Develop functional and code coverage models and track verification completeness.
• Collaborate with RTL designers and architects to understand specifications and resolve design issues.
• Develop automation and productivity tools using Python, Perl, and TCL.
• Write and execute low-level tests using RISC-V or ARM Assembly and C/C++ where required.
• Support regression infrastructure, test execution, failure triage, and verification reporting.
• Contribute to verification methodology improvements, reusable infrastructure, and automation initiatives.
• Support advanced verification activities involving power-aware verification using UPF/CPF, where applicable.
• Contribute to verification of high-speed interfaces such as PCIe, CXL, and DDR.
• Support emulation-based verification using platforms such as Palladium, Veloce, or Zebu, where required.
• Mentor junior verification engineers and contribute to technical reviews and knowledge sharing.

WHAT MAKES YOU A GREAT FIT

• 5+ years of total ASIC/SoC Design Verification experience, including at least 2+ years of dedicated CPU verification experience.
• Strong hands-on expertise in SystemVerilog and UVM.
• Practical CPU verification experience with RISC-V, ARM, x86, or custom processor architectures.
• Strong understanding of CPU architecture, pipeline execution, cache coherency, memory ordering, interrupts, and exceptions.
• Hands-on experience with AMBA protocols, particularly AXI, AHB, ACE, and/or CHI.
• Experience with EDA simulation tools such as Synopsys VCS, Cadence Xcelium, or Siemens Questa.
• Strong experience developing UVM testbenches, sequences, monitors, scoreboards, assertions, and coverage models.
• Working knowledge of RISC-V/ARM Assembly, C/C++, Python, Perl, and TCL scripting.
• Understanding of out-of-order execution and modern processor verification concepts.
• Strong debugging, analytical, and problem-solving skills.
• Ability to analyse complex simulation failures and drive issues through resolution.
• Strong communication and collaboration skills across Design, Architecture, Firmware, and Verification teams.
• Experience with UPF/CPF and power-aware verification is an advantage.
• Exposure to PCIe, CXL, DDR, or other high-speed interconnects is an advantage.
• Experience with Palladium, Veloce, Zebu, or other emulation platforms is an advantage.
• B.Tech/M.Tech in Electronics, VLSI, Computer Engineering, or a related discipline is preferred.