Design Verification Lead

Weekday; Bengaluru; On-site; INR 3,500,000 - 6,000,000; Full time

Job summary

Weekday in Bengaluru seeks a Senior Design Verification Engineer to drive verification for complex IP and SoC designs, leveraging SystemVerilog and UVM.

The ideal candidate has 7+ years of hands-on experience, develops reusable verification environments, creates verification plans, and drives coverage closure across multiple projects.

Qualifications

• 7+ years of experience in ASIC/SoC/IP verification
• Proven track record across IP/SoC verification projects
• Strong SystemVerilog and UVM methodology
• Experience with verification environments and VIPs

Responsibilities

• Develop and execute verification strategies and plans for IP/SoC projects
• Translate requirements into verification tests, scenarios, and coverage objectives
• Build reusable SystemVerilog/UVM testbenches and components
• Configure and debug functional and gate-level simulations
• Maintain regression environments for large verification programs
• Analyze failures and drive root-cause analysis with RTL/design teams
• Evaluate third-party VIPs and integrate into verification environments
• Mentor junior engineers and contribute to best practices

Skills

SystemVerilog

UVM

IP/SoC verification

Verification planning

Debugging

Coverage analysis

Python scripting

RTL concepts

Third-party VIP integration

Job description

Industry: Semiconductor Manufacturing

Seniority level: Mid-Senior level

Experience: 7+ yrs

Location: Bengaluru

Job Type: Full-time

₹35,00,000 - ₹60,00,000 a year

We are looking for an experiencedSenior Design Verification Engineerwith strong expertise inSystemVerilog (SV) and UVM-based verificationto drive verification activities for complex IP and SoC designs.

The ideal candidate will have hands-on experience executing multipleIP and SoC verification projects, developing robust verification environments, creating verification plans, debugging functional and gate-level simulations, and driving coverage closure. Experience with at least one industry-standard protocol such asEthernet, PCIe, MIPI, USB, AXI, RISC-V, AMBA, or DDRis required.

Requirements

Key Responsibilities

• Develop and execute comprehensivedesign verification strategies and plansfor IP and SoC projects.
• Translate functional and technical requirements into detailedverification plans, test scenarios, and coverage objectives.
• Develop scalable and reusableSystemVerilog/UVM verification environments.
• Build UVM components including testbenches, agents, drivers, monitors, sequencers, scoreboards, and coverage models.
• Set up, configure, execute, and debugfunctional and gate-level simulations.
• Develop and maintain automated regression environments for large verification programs.
• Analyze simulation failures, identify root causes, and collaborate with RTL and design teams to resolve issues.
• Verify designs using industry-standard protocols such asEthernet, PCIe, MIPI, USB, AXI, RISC-V, AMBA, DDR, or equivalent protocols.
• Evaluate, integrate, configure, and validatethird-party Verification IP (VIP).
• Develop effective test strategies for functional, corner-case, error, and protocol-specific scenarios.
• Performfunctional and code coverage analysisand drive coverage closure.
• Identify verification gaps and develop additional tests, assertions, or coverage models where required.
• Review simulation results, regression trends, coverage reports, and verification metrics.
• Improve verification infrastructure, methodologies, automation, and regression efficiency.
• Collaborate with RTL, architecture, firmware, emulation, and other engineering teams throughout the verification lifecycle.
• Participate in design and verification reviews and contribute technical recommendations.
• Maintain verification documentation, test plans, environments, results, and closure reports.
• Mentor junior verification engineers and contribute to verification best practices and methodology improvements.

What Makes You a Great Fit

• 7+ years of professional experiencein ASIC, SoC, IP, or semiconductor design verification.
• Proven experience executingat least 3 IP or SoC verification projectsfrom planning through verification closure.
• Strong hands-on expertise inSystemVerilog and UVM methodology.
• Experience developing and maintaining reusable UVM-based verification environments.
• Strong experience translating functional requirements intoverification plans and test strategies.
• Hands-on experience setting up and debuggingfunctional and/or gate-level simulations.
• Strong experience developing verification environments and automatedregression setups.
• Practical experience withfunctional coverage, code coverage, coverage analysis, and coverage closure.
• Experience evaluating and integratingthird-party VIPsinto verification environments.
• Strong understanding of digital design, RTL concepts, simulation, debugging, and verification methodologies.
• Hands-on experience with at least one industry-standard protocol such asEthernet, PCIe, MIPI, USB, AXI, RISC-V, AMBA, or DDR.
• Strong debugging, analytical, and problem-solving capabilities.
• Ability to investigate complex simulation failures and identify root causes across RTL, testbench, and verification environments.
• Experience with industry-standard simulators and verification tools is desirable.
• Strong scripting or automation skills using languages such asPython, Perl, or Tclare an advantage.
• Excellent communication and collaboration skills with the ability to work effectively across design and verification teams.
• Strong ownership mindset with the ability to independently drive verification activities fromplanning through coverage closure.