IP/SOC Verification Engineer

Bitsilica; Bengaluru; On-site; INR 4,500,000 - 9,000,000; Full time

Job summary

Bitsilica in Bengaluru, India seeks an experienced Design Verification Manager to lead DV for IP, subsystem, SoC and ASIC designs. You will shape verification strategies, drive reusable UVM environments, and oversee complex protocol and memory interfaces.

The role demands deep SystemVerilog/UVM expertise, AMBA protocol knowledge, and a proven ability to lead and deliver across multiple concurrent programs.

Qualifications

• Experience in IP/SoC/ASIC verification required.
• Strong SystemVerilog/UVM expertise and AMBA protocol knowledge.
• Proven track record leading verification teams to closure.

Responsibilities

• Lead and manage DV teams for IP, subsystem, and SoC/ASIC verification projects.
• Define verification strategies, test plans, coverage goals, and timelines.
• Develop scalable SystemVerilog/UVM environments and reusable components.
• Oversee subsystem interfaces, memory subsystems, RAL, and protocol checks.
• Guide constrained-random, assertion-based, and coverage-driven verification.
• Ensure verification closure with coverage, assertions, regressions, and debugging.

Skills

SystemVerilog

UVM

AMBA protocols

Leadership

Education

BE/BTech/ME/MTech in Computer Science, Electronics, Electrical Engineering, or related field

Job description

We are seeking an experienced and results-driven Design Verification Manager to lead verification activities for complex IP, subsystem, SoC, and ASIC designs. The ideal candidate will possess strong technical expertise in SystemVerilog/UVM-based verification methodologies, SoC integration, AMBA protocols, and team leadership.

Key Responsibilities

• Lead and manage Design Verification teams for IP, subsystem, and SoC/ASIC verification projects.
• Define verification methodologies, strategies, test plans, coverage goals, and execution timelines.
• Drive development of scalable and reusable SystemVerilog/UVM-based verification environments.
• Oversee verification of subsystem interfaces, Register Abstraction Layer (RAL), memory subsystems, and protocol compliance.
• Guide teams in developing constrained-random, assertion-based, and coverage-driven verification environments.
• Ensure successful verification closure including functional coverage, code coverage, assertions, regressions, and debug.
• Manage project schedules, resource allocation, priorities, and risk mitigation across multiple concurrent programs.

Education & Experience

• BE/BTech/ME/MTech in Computer Science, Electronics, Electrical Engineering, or related field.
• 6 to 15+ years of hands-on experience in IP, SoC, or ASIC verification.