PMTS - Design Verification Engineer: SOC Focused

Tsavorite Scalable Intelligence; Bengaluru; On-site; INR 1,800,000 - 2,800,000; Full time

Job summary

Tsavorite Scalable Intelligence is seeking a Senior SoC Verification Engineer focused on PCIe and CXL to lead end-to-end data-path validation for ARM-based designs.

You will drive full-chip DV plans, develop UVM tests, and collaborate with RTL, architecture, and firmware teams to ensure correctness, performance, and scalability across multi-chip systems. The role requires 14+ years of relevant experience and a proven track record in high-performance SoC verification.

Qualifications

• Strong knowledge of PCIe protocol (transaction and data path).
• Experience with CXL (io/cache/mem).
• Proficiency in SystemVerilog and UVM.

Responsibilities

• Validate PCIe/CXL data path at full-chip and multi-chip level.
• Validate CXL data flows and host–device coherency.
• Execute SoC-level DV plans for PCIe/CXL flows.
• Implement UVM-based tests including mid-transaction reset.
• Build scoreboards and data integrity checks under high throughput.
• Capture waveforms and transaction traces for debugging.
• Firmware interaction and collaboration with RTL, architecture, and firmware teams.

Skills

PCIe protocol

CXL

SystemVerilog / UVM

Job description

SMTS -Design Verification Engineer: SOC Focused [Experience Level 14+]

Founded in 2023,by Industry veterans HQ in California,US

Company Description

We are looking for exceptional talent and leadership to join , the world’s first company developing Agentic Silicon for powering the future of AI.

Founded in 2023, our team consists of 90+ highly skilled engineers from leading companies such as Intel, Marvell, Nvidia, Qualcomm, Cisco, AMD, Apple etc. We have deep customer engagements across America, Europe, and Asia, and demonstrated functional prototypes to prove our concept and vision.Principal Design Verification Engineer: SOC Focused

Job Description

We are seeking a SoC Verification Engineer to work on end-to-end data-path verification for high-performance ARM-based SoCs. This role focuses on validating correctness, coherency, performance, and scalability of data movement across PCIe and CXL fabrics, from IP blocks through interconnect to CPUs and memory, at chip and multi-chip system levels. This is full-chip, cross-IP, real-silicon mindset verification.

Key Responsibilities

• Validate PCIe/CXL Data path at full chip and multichip level.
• Validate CXL data flows, Host–device coherency interactions
• Execute SoC-level DV plans for flows pertaining to PCIe / CXL
• Implement:
• UVM-based system tests including mid-transaction reset, contention scenario
• Scoreboards and data integrity checks under high throughput, concurrent traffic
• Waveforms
• Transaction traces
• Firmware interaction
• Collaborate with RTL, architecture, and firmware teams

Required Skills & Experience

• Strong knowledge of:
• PCIe protocol (transaction & data path focus)
• CXL (io/cache/mem)
• Proficiency in:
• SystemVerilog / UVM

Preferred Qualifications

• Multi-chip / chiplet system experience
• Exposure to real workloads (storage, networking, AI accelerators)