Design And Verification Engineer

Object Technology Solutions

Ahmedabad District, Vadodara

On-site

INR 900,000 - 1,500,000

Full time

14 days+

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Job summary

Object Technology Solutions is seeking a skilled ASIC Verification Engineer with 3-5 years of hands-on experience to join our hardware verification team in India. You will apply SystemVerilog, UVM, and coverage-driven methods to verify ASIC subsystems and IPs, and you will build testbenches from scratch.

You should have a strong grasp of SV, SVA, constrained randomization, and DUT integration. Cadence or Synopsys tool experience is required, along with scripting skills in Shell or Makefile to

Qualifications

  • Bachelor's or Master's degree in Electronics, Electrical Engineering, Computer Science, or a related field.
  • 3-5 years of hands‑on experience in ASIC Design Verification.
  • Strong expertise in SystemVerilog (SV).
  • UVM Methodology.
  • Constrained Randomization and Coverage‑Driven Verification.
  • SystemVerilog Assertion (SVA).
  • Hands‑on experience in ASIC - Subsystem, or IP Verification.
  • Testbench development from scratch.
  • DUT integration and verification environment development.
  • Experience with Cadence or Synopsys tools.
  • Good scripting skills using Shell Scripting or Makefile.

Skills

SystemVerilog SV
UVM Methodology
Constrained Randomization
Coverage-Driven Verification
SystemVerilog Assertion
ASIC Verification
Testbench Development
DUT Integration
Scripting Skills

Education

Bachelor's or Master's degree in Electronics, Electrical Engineering, Computer Science, or a related field

Tools

Cadence tools
Synopsys tools
Makefile
Shell scripting

Job description

Required Qualifications

  • Bachelor's or Master's degree in Electronics, Electrical Engineering, Computer Science, or a related field.
  • 3-5 years of hands‑on experience in ASIC Design Verification.
  • Strong expertise in:
  • SystemVerilog (SV)
  • UVM Methodology
  • Constrained Randomization and Coverage‑Driven Verification
  • SystemVerilog Assertion (SVA)
  • Hands‑on experience in:
  • ASIC - Subsystem, or IP Verification
  • Testbench development from scratch
  • DUT integration and verification environment development
  • Experience with industry‑standard EDA tools from Cadence or Synopsys.
  • Good scripting skills using one or more of the following:
  • Shell Scripting
  • Makefile
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