Lead Design Verification Engineer

eInfochips; Hyderabad, Pune District, Bengaluru; On-site; INR 1,400,000 - 2,100,000; Full time

Job summary

eInfochips in Hyderabad is seeking an experienced ASIC/SoC Design Verification engineer to drive end-to-end verification across complex IPs and subsystems. You will contribute to test plan creation, coverage models, and regression management.

Build scalable UVM-based verification environments, debug intricate issues, and collaborate with cross-functional teams using tools like Verdi and SimVision.

Qualifications

• Experience with Verilog/SystemVerilog in ASIC verification.
• Hands-on with UVM methodology and testbench development.
• Proficient in C/C++ and DPI integration.
• Scripting skills in Python or Perl; Makefile knowledge is a plus.
• Strong debugging and root-cause analysis abilities.
• Solid understanding of SoC/ASIC design flow and verification methodologies.

Responsibilities

• End-to-end ASIC/SoC Design Verification.
• Build scalable UVM-based verification environments.
• Develop test plans, test cases, assertions and coverage models.
• Regression management and coverage closure.
• Debug complex issues using tools like Verdi and SimVision.

Skills

Verilog

SystemVerilog

UVM

C/C++

DPI integration

Python

Perl

Makefile

Debugging

SoC/ASIC design flow

Tools

Verdi

SimVision

Job description

What Youll Be Working On

• End-to-end ASIC/SoC Design Verification
• Building scalable UVM-based verification environments
• Developing test plans, test cases, assertions & functional coverage models
• Regression management and coverage closure
• Debugging complex issues using tools like Verdi / Sim Vision

Technical Expertise We’re Looking For

• Strong hands-on experience in Verilog / System Verilog
• Solid experience with UVM methodology
• C/C++, DPI integration knowledge
• Scripting skills in Python / Perl / Makefile
• Strong debugging and root-cause analysis skills
• Good understanding of SoC/ASIC design flow

Protocol Experience (Preferred)

• Hands-on experience in high-speed interfaces such as PCIe (Gen4/Gen5)
• Experience or exposure to UCIe (Universal Chiplet Interconnect Express)protocol
• Knowledge of AMBA USB, DDR, SPI or other communication protocols