Senior Design Lead - DFT

HCL Technologies Limited; India; On-site; INR 2,000,000 - 4,000,000; Full time

Job summary

HCL Technologies Limited is seeking a Senior Design Lead to drive end-to-end DFT solutions for large-scale projects. You will manage team deliverables and collaborate across design teams to embed DFT throughout the design flow.

The role requires 4–10 years of DFT experience with ASIC/SoC exposure, strong analytical skills, and excellent communication for cross-functional teamwork. On-site India location with opportunities to influence complex digital architectures.

Qualifications

• Bachelors in Electrical/Computer Engineering or related field.
• 4-10 years of experience in Design for Testability (DFT) or related field.
• Basic understanding of digital design: combinational and sequential logic.
• Working knowledge of DFT concepts (scan insertion, ATPG, fault coverage).
• Familiarity with DFT tools and methodologies is a plus.
• Ability to learn quickly and adapt to new technologies.
• Strong analytical and problem-solving skills.
• Excellent communication and collaboration abilities.

Responsibilities

• Collaborate with design engineers to incorporate DFT techniques in the design flow.
• Develop and implement DFT strategies for high test coverage and fault detection.
• Use DFT tools to enhance testability of digital circuits.
• Write and maintain DFT test plans and reports.
• Analyze test results and identify potential design issues.
• Participate in design reviews and provide DFT feasibility feedback.
• Stay up-to-date with latest DFT methodologies and tools.

Skills

DFT concepts

Digital design principles

Analytical skills

Communication skills

Team collaboration

Education

Bachelor's degree in Electrical Engineering or related field

Tools

Scan insertion

ATPG

DFT tools

Job description

The Senior Design Lead drive end-to-end DFT solutions for large-scale projects and manage team deliverables.

Key Responsibilities

Responsibilities:

• Collaborate with design engineers to incorporate DFT techniques throughout the design flow


• Develop and implement DFT strategies for achieving high test coverage and fault detection


• Utilize DFT tools (scan insertion, ATPG) to enhance the testability of digital circuits


• Write and maintain DFT test plans and reports


• Analyze test results and identify potential design issues


• Participate in design reviews and provide feedback on DFT feasibility


• Stay up-to-date with the latest advancements in DFT methodologies and tools

Skill Requirements

Qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field


• 4-10 years of experience in Design for Testability (DFT) or a related field (experience with ASIC/SoC design a plus)


• Basic understanding of digital design principles (combinational logic, sequential logic)


• Working knowledge of DFT concepts (scan insertion, ATPG, fault coverage)


• Familiarity with DFT tools and methodologies is a plus


• Ability to learn quickly and adapt to new technologies


• Strong analytical and problem-solving skills


• Excellent communication and collaboration skills to work effectively in a team environment

Other Requirements

1. Optional But Valuable Certifications: Certified Usability Analyst (Cua), Ux Design Professional Certificate, Or Equivalent Design Certifications.

At HCLTech, you'll supercharge your potential. You'll find your career. And you'll find your spark. All at a place that knows that helping its customers stay on top starts by putting its people first.

HCLTech is a global technology company, home to more than 223,000 people across 60 countries, delivering industry-leading capabilities centered around digital, engineering, cloud and AI, powered by a broad portfolio of technology services and products. We work with clients across all major verticals, providing industry solutions for Financial Services, Manufacturing, Life Sciences and Healthcare, Technology and Services, Telecom and Media, Retail and CPG, and Public Services. Consolidated revenues as of 12 months ending June 2026totaled $14.8billion.