Senior Director - DFT

844 Altera Semiconductor Technology India Pvt. Ltd.; Bengaluru; On-site; INR 6,500,000 - 11,000,000; Full time

Job summary

844 Altera Semiconductor Technology India Pvt. Ltd. in Bengaluru, Karnataka, seeks an experienced DFT Technical Leader to drive advanced Design-for-Test (DFT) methodologies for next‑gen FPGA products.

You will set the DFT architecture, oversee implementation, and build a high-performing DFT engineering team. You will collaborate with RTL, timing, silicon validation, and manufacturing to improve test readiness, accelerate bring‑up, and drive measurable yield improvements across product

Qualifications

• Bachelor's degree in Electrical/Computer Engineering or related field with 12+ years in DFT development and deployment.

Responsibilities

• Define and drive DFT architecture and implementation strategy for FPGA products from spec to tapeout, scalable across generations.
• Serve as technical authority for DFT, guiding decisions and mentoring engineers.
• Define DFT strategies across FPGA subsystems including programmable logic, memories, IP, and configuration infra.
• Lead hierarchical multi-die DFT architectures for chiplet-based products and test approaches.
• Partner with RTL, physical design, silicon validation, product engineering, and manufacturing to embed DFT requirements throughout development.
• Drive improvements in test readiness, coverage, fault detection, and yield via DFT architecture, automation, and debugging.
• Lead cross-organizational DFT issue resolution post-silicon: bring-up, failure analysis, and yield improvements.
• Identify emerging DFT technologies and influence roadmaps and engineering processes.
• Build and develop a DFT team, own resource planning and vendor strategy.

Skills

DFT architecture

ATPG

MBIST/BISR

JTAG/boundary scan

DFT verification

silicon bring‑up/debug

scripting (Python TCL Perl)

leadership

Education

Bachelor's degree in Electrical/Computer Engineering

Tools

Tessent

Modus

IEEE 1149.1

IEEE 1687 (IJTAG)

IEEE 1838

Job description

Altera is seeking an experienced DFT Technical Leader to drive advanced Design-for-Test (DFT) methodologies across next-generation FPGA products. You will be the technical authority for DFT architecture, methodology, and implementation while building and leading the DFT engineering team. You will work across the design, silicon, and manufacturing organizations to improve test readiness, accelerate bring-up, and drive measurable yield improvement.

Responsibilities

• Define and drive DFT architecture, methodology, and implementation strategy for next-generation FPGA products from specification through tapeout, silicon bring-up, and production, with methodologies that scale across product generations and design teams.
• Serve as the technical authority and subject matter expert for DFT across the organization, guiding complex technical decisions and mentoring engineers on advanced DFT concepts, methodologies, and implementation challenges.
• Define DFT strategies across key FPGA subsystems, including programmable logic, embedded memories, hardened IP, configuration infrastructure, and high-speed I/O.
• Define hierarchical and multi-die DFT architectures for chiplet-based and 2.5D/3D-packaged products, including die-to-die interface test, streaming scan network approaches, and known-good-die strategy.
• Partner closely with RTL and physical design, verification, silicon validation, product engineering, manufacturing, and test teams to ensure DFT requirements are incorporated throughout the product development lifecycle.
• Drive improvements in test readiness, test coverage, fault detection, test efficiency, and overall testability, and reduce silicon-to-product bring-up time through DFT architecture, automation, and debug capability.
• Lead technical resolution of complex, cross-organizational DFT issues post-silicon: test-pattern bring-up, failure diagnosis, correlation, and yield improvement.
• Identify emerging DFT technologies, standards, and industry trends, and influence technical roadmaps, architecture decisions, and engineering processes accordingly.
• Build, lead, and develop a team of DFT engineers (hiring, technical coaching, performance management, and career development), and own DFT resource planning, execution commitments across concurrent programs, and EDA tool and vendor strategy.
• Define and track key DFT metrics (test coverage, test-to-product bring-up time, test efficiency, and yield), and represent DFT technical strategy and recommendations to senior engineering leadership.

Job Details

Job Type: Regular Shift: Shift 1 (India) Primary Location: Bengaluru, Karnataka, India Additional Locations:

Qualifications

Minimum Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical field, with 15+ years in semiconductor engineering including 12+ years of hands‑on DFT development, implementation, and deployment (13+ years with an MS, 10+ years with a PhD).
• Deep hands‑on expertise in DFT architecture and implementation, including scan and test compression, ATPG, MBIST/BISR, JTAG/boundary scan, DFT verification, and silicon bring‑up/debug, on complex ASIC, SoC, or FPGA products.
• Demonstrated expertise with industry‑standard DFT tooling and standards, including commercial ATPG and DFT insertion tools (e.g., Tessent, Modus), IEEE 1149.1 boundary scan, IEEE 1687 (IJTAG), and IEEE 1838, plus a track record of adopting or advancing new DFT technologies.
• Demonstrated improvement of silicon bring‑up, test readiness, test coverage, manufacturing test, or product yield through DFT.
• Proficiency in scripting and automation (Python, TCL, and/or Perl) for DFT flow, tool, and methodology development.
• Experience leading engineers as a manager or team lead (hiring, technical mentoring, and performance development), and influencing architecture, methodology, and technical direction across multiple engineering teams.
• Strong understanding of semiconductor manufacturing, test, yield, and product development processes, with excellent cross‑functional communication skills.

Preferred Qualifications

• Experience with FPGA‑specific DFT challenges in high‑volume manufacturing, including programmable fabric, configuration memory, and SerDes.
• Experience reducing test time and cost of test on production ATE platforms (e.g., Advantest V93000, Teradyne UltraFLEX) and driving DPPM and test‑quality targets.
• Experience with advanced process technologies, multiple product generations, and increasingly complex SoC/FPGA architectures.
• External recognition as a DFT expert: patents, publications, conference presentations (e.g., ITC, VTS), or participation in industry standards bodies or working groups.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

About Altera

Altera: Accelerating Innovators Altera provides leadership programmable solutions that are easy-to-use and deploy in applications from cloud to edge, offering limitless AI possibilities. Our end-to-end broad portfolio of products including FPGAs, CPLDs, Intellectual Property, development tools, System on Modules, SmartNICs and IPUs provide the flexibility to accelerate innovation. Altera is helping to shape the future through pioneering innovation that unlocks extraordinary possibilities for everyone on the planet.