Sr. DFT Lead

Texas Instruments; Bengaluru; On-site; INR 3,500,000 - 7,000,000; Full time

Job summary

Texas Instruments in Bengaluru seeks a DFT Lead with 8+ years of experience to drive design-for-test strategies across product development. You will lead a team of DFT engineers, influence design decisions, and ensure robust, testable semiconductor designs.

You will define specifications for scan, ATPG, boundary scan, memory BIST, and JTAG, collaborate with design and manufacturing, and push continuous improvement in DFT methodologies and tooling.

Qualifications

• At least 8 years of DFT experience in digital and mixed-signal design.
• Experience with ATPG, scan insertion, and test pattern generation.
• Hands-on with DFT-related EDA tools including scan compression, boundary scan, memory BIST, and JTAG.
• Familiar with silicon bring-up and post-silicon debug.
• Strong analytical, leadership, and communication skills.
• Bachelor's or Master's degree in Electrical/Computer Engineering or related field.

Responsibilities

• Develop and implement DFT strategies to maximize test coverage and yield.
• Define DFT specifications for scan, compression, boundary scan, and memory BIST.
• Lead and mentor DFT engineers and collaborate with design, verification, and manufacturing.
• Drive continuous improvement of DFT methodologies and tooling.
• Perform DFT sign-off activities including coverage and ATPG fault analysis.
• Stay updated on industry trends in semiconductor testing.

Skills

DFT Expertise

ATPG Expertise

Boundary Scan

Memory BIST

JTAG

Python

Leadership

Education

Bachelor's or Master's in Electrical/Computer Engineering

Tools

DFT EDA Tools

Job description

We are seeking a highly skilled and experienced DFT Lead to join our dynamic team. As a DFT Lead, you will play a pivotal role in ensuring the successful implementation of Design-for-Test (DFT) strategies and methodologies across product development lifecycle. With at least 8 years of relevant experience, you will lead and guide a team of DFT engineers to deliver high-quality, testable, and efficient designs. Your expertise in DFT techniques, tools, and industry standards will be critical in achieving our goal of producing robust and reliable semiconductor products.

Responsibilities:

• Develop and execute DFT methodologies, strategies, and guidelines to maximize test coverage, reduce test cost, and optimize production yield.
• Define and review DFT specifications, including scan, test compression, boundary scan, memory BIST, and ATPG patterns, ensuring compliance with industry standards.
• Evaluate and select appropriate DFT methodologies, considering design complexity, test coverage requirements, and time-to-market constraints.
• Work closely with the design team to influence design decisions and ensure DFT requirements are met without compromising performance, power, or area.
• Lead and manage the DFT team, providing technical guidance and mentorship to engineers, ensuring their professional growth and development.
• Collaborate with cross-functional teams, including design, verification, and manufacturing, to define DFT requirements and drive DFT implementation throughout the product lifecycle.
• Drive continuous improvement initiatives to enhance DFT methodologies, tools, and processes, aiming for increased efficiency, quality, and reliability of DFT implementation.
• Perform DFT sign-off activities, including DFT coverage analysis, ATPG fault coverage analysis, DFT-related timing analysis, first-pass silicon bring-up and post-silicon debug.
• Stay abreast of industry trends, emerging DFT techniques, and advancements in semiconductor testing, and apply relevant knowledge to improve DFT practices within the organization.

Requirements:

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
• Minimum of 8 years of experience in DFT, with focus on digital and mixed signal designs in the semiconductor industry.
• Experience with ATPG, scan insertion, and test pattern generation for high-complexity designs.
• Hands-on experience with DFT-related EDA tools and methodologies, including scan compression, boundary scan, memory BIST, and JTAG.
• Familiarity with silicon bring-up and post-silicon debug.
• Strong knowledge of DFT techniques, methodologies, and industry standards, such as IEEE 1149.1.
• Experience in scripting languages, such as Perl or Python, for automation and data analysis is desirable.
• Strong analytical and problem-solving skills, with the ability to identify and address DFT-related issues and challenges.
• Excellent communication and leadership abilities, with a track record of successfully leading teams and collaborating with cross-functional stakeholders.
• Self-motivated and detail-oriented, with a commitment to delivering high-quality results within established timelines.