Sr Design Verification Eng

Lattice Semiconductor; Pune District; On-site; INR 1,800,000 - 2,400,000; Full time

Job summary

Lattice Semiconductor in India is seeking a senior DV verification engineer to join our Silicon Engineering team. You will verify complex FPGA/SoC IP, develop reusable UVM test benches, and drive coverage-driven verification across HW/FW interfaces.

The role requires 6+ years of DV experience, strong SystemVerilog/UVM, and proven ASIC verification from concept to tape-out, with IPs like PCI Express, Ethernet, or USB. Collaboration with design, architecture, SW, and FW teams is essential.

Qualifications

• BS/MS degree in EE/CS or equivalent required.
• 6+ years DV experience with at least 2+ years leading complex IP verification.
• Proven track record in full ASIC verification from concept to tape‑out.
• Strong SystemVerilog and UVM knowledge.
• Experience verifying IPs like PCI Express, Ethernet or USB in UVM.
• Experience with AMBA-based IP verification and firmware interactions.
• Exposure to low power design and UPF integration.

Responsibilities

• Verify complex FPGA/ASIC IPs within SOC verification environment.
• Develop reusable UVM test benches and verification plans.
• Collaborate with design, architecture, SW, FW teams to integrate verification.
• Ensure coverage targets are met and diagnose HW/FW issues.

Skills

SystemVerilog

UVM

IP verification

PCI Express

Ethernet

USB

AMBA bus

Low power design (UPF)

Firmware verification

DV experience (ASIC)

Education

BS/MS Electrical Engineering, Computer Science, Computer Systems Engineering, or equivalent degree

Job description

Lattice Overview

There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world‑class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality. Energy feeds on energy. If you flourish in a fast paced, results‑oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.

Job Description

Inviting candidates with a passion for invention and self‑challenge. This position gives you an opportunity to be a part of one of the most cutting edge and key projects that Lattice’s Silicon Engineering team has embarked upon to date. As part of our team, you will have the opportunity to contribute to verifying complex FPGAs. This team will allow you to integrate multiple sophisticated IP level Design and Verification (DV) environments, craft highly reusable best‑in‑class UVM TB, implement effective coverage driven and directed test cases, deploy new tools and implement methodologies to improve quality of tape‑out readiness. By collaborating with other product development teams across Lattice, you can push the industry boundaries of what FPGA systems can do and improve the product experience for our customers across the world! You will be able to learn all aspects of a FPGA, different types of SOC architecture, many highspeed layered protocols, industry’s standard methodologies on low power architecture, best in class DV methodology, verification on accelerated platforms, FW‑HW interactions, complexities of FPGA and SOC debug architecture, etc. You’ll be at the center of the design verification effort within our silicon design SOC verification team responsible for crafting and productizing state‑of‑the‑art FPGAs. This position requires someone comfortable will all areas of FPGA design verification engineering. Someone that thrives in a dynamic multi‑functional organization and is not afraid to take on challenges and solve complex problems using state of the art verification methodologies.

Required Skills

• BS/MS Electrical Engineering, Computer Science, Computer Systems Engineering, or equivalent degree
• At least 6+ years DV experience out of which 2+ years as leading a complex IP verification
• Proven track record of working full ASIC verification from concept to tape‑out
• Advanced knowledge of System Verilog and UVM methodology
• Hands‑on verification experience in verifying IPs like PCIExpress, Ethernet or USB in UVM environment will be big plus.
• Hands‑on verification experience in verifying IPs using AMBA bus architecture in UVM environment.
• Hands‑on verification experience in verifying the firmware used for SOC functions
• Exposure on working with low power design, UPF integration, boot‑up, power‑cycling, HW/FW interaction verification.
• Ability to create IP level module and sub‑system verification plans, TBs, portable test benches, sequences, verification infrastructure.
• Develop UVM based highly reusable test benches and integrate complex multi‑instance VIPs, sub‑system test benches and verification suites at SOC level, and achieve targeted coverage
• Work with design, architecture, SW, FW, and IP delivery teams to efficiently integrate and verify overall FPGA design.
• Should be a great team member with excellent communication and problem‑solving skills and the desire to seek diverse challenges.

Company Overview

Lattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry. Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry. Lattice is an international, service‑driven developer of innovative low cost, low power programmable design solutions. Our global workforce, some 1,000+ strong, shares a total commitment to customer success and an unbending will to win. For more information about how our FPGA, CPLD and programmable power management devices help our customers unlock their innovation, visit www.latticesemi.com. You can also follow us via Twitter, Facebook, or RSS.

Core Values

GROWTH

We foster a culture where everyone strives for continuous learning and development. We challenge ourselves to boldly deliver exceptional growth and value for customers and shareholders.

RELIABILITY

Our customers trust us to deliver, and we take that responsibility seriously. By committing ourselves to dependable supply, support, and solutions, we build strong collaboration that lasts and thrives.

EXECUTION

Innovation turns great ideas into results. Together, we create differentiated products and solutions through disciplined planning, decisiveness, and timely delivery with uncompromising quality.

ACCOUNTABILITY

We own our actions and outcomes: holding ourselves to the highest standards, agilely adapting to change, delivering on our commitments, and empowering each other to drive our success.

TRANSPARENCY

Openness builds trust. We lead with integrity and candor, facing hard facts and embracing tough conversations with clear communication, decisive action, and open honesty at each level.

About Lattice Semiconductor

Lattice Semiconductor (NASDAQ: LSCC) is the low power programmable leader. For over 40 years, Lattice has driven innovation in the semiconductor industry. Our compact, power‑efficient field programmable gate arrays (FPGAs) are essential to building a secure, intelligent, and connected world. Lattice is the #1 supplier of small FPGAs worldwide, with the largest installed base in the industry. Our solutions are trusted by over 11,000 customers globally, spanning the compute, communications, industrial, and embedded markets.

Headquarters and Operations

Founded in 1983 in Oregon’s Silicon Forest, Lattice has grown into a global leader with a passionate team dedicated to pushing the boundaries of programmable logic and fostering a culture of innovation. Headquartered in Portland, Oregon with major operations in San Jose, California, Shanghai, China, and Manilla, Philippines.

Applications are welcome from all qualified candidates. #LI-DNP

Additional Information

This position requires a successful background and reference checks and satisfactory proof of your right to work in: India