Senior Custom IC Layout Engineer

MetAntz; Hyderabad; On-site; INR 3,500,000 - 7,500,000; Full time

Job summary

MetAntz seeks a senior IC layout engineer to lead full-custom memory IP layout in cutting-edge CMOS tech. You will drive SRAM macro layout, floorplanning, schematic-to-layout translation, and rigorous verification with Calibre/ICV.

You will collaborate with circuit, CAD, and foundry teams to ensure reliability, density, and tapeout readiness while mentoring junior engineers in a fast-paced, growth-oriented environment.

Qualifications

• BSEE or equivalent experience is required.
• 10+ years custom IC layout experience, including 5+ years SRAM/memory IP layout.
• Hands-on with advanced CMOS tech (FinFET/GAA) 5nm/3nm.
• Solid SRAM and memory layout principles.
• Cadence Virtuoso for custom layout creation.
• Extensive DRC/LVS debugging with Calibre/ICV.
• Experience in floorplanning, block-level routing, macro assembly, pin planning, boundary management.
• Familiarity with advanced-node layout limits and LOD/density/DFM effects.
• Ability to collaborate with circuit build, physical build, CAD, and foundry teams.
• Nice to have knowledge of layout automation or AI tools.

Responsibilities

• Manage the complete custom layout process for SRAM bitcell arrays, memory periphery, test structures, and memory macros in advanced CMOS technologies.
• Develop and improve floorplans for SRAM and memory blocks, covering array layout, periphery positioning, power grid design, routing channels, and macro assembly.
• Carry out, debug, and complete DRC, LVS, ERC, antenna, and related physical verification checks with tools like Calibre, ICV, or similar workflows.
• Support EM, IR review, power integrity, density, fill, DFM, dummy insertion, LDE, and tapeout requirements.
• Collaborate with circuit designers to convert schematics into layouts, ensuring matching, symmetry, shielding, parasitic targets, and reliability constraints.
• Collaborate with PnR and integration teams to resolve top-level DRC, LVS, pin access, boundary, routing, power-grid, and macro-integration issues.
• Implement and advance layout methodology, checklists, reusable practices, and quality standards for consistent memory IP delivery.
• Coordinate with foundry, CAD, and methodology teams on rule interpretation, deck behavior, waivers, and advanced-node process constraints.
• Review layouts, mentor junior engineers, and raise layout quality and execution rigor across the team.

Skills

10+ years IC layout

SRAM/memory IP layout

FinFET/GAA node experience

SRAM/memory layout principles

Cadence Virtuoso

DRC/LVS using Calibre/ICV

Floorplanning & routing

Top-level verification

Cross-team collaboration

Layout automation/AI tools

Education

BSEE or equivalent experience

Tools

Calibre

ICV

Job description

Company Description

MetAntz is focused on bridging the gap between skilled talent and global career opportunities. The company empowers students and professionals by connecting them with high-paying, growth-focused roles around the world. MetAntz is committed to helping candidates become more employable, increase their earning potential, and accelerate their career trajectories. By partnering with organizations that value expertise and innovation, the company creates pathways for long-term professional success. Team members join a mission-driven environment that is actively shaping the future of work, one opportunity at a time.

Roles and Responsibilities

• Manage the complete custom layout process for SRAM bitcell arrays, memory periphery, test structures, and memory macros in advanced CMOS technologies.
• Develop and improve floorplans for SRAM and memory blocks, covering array layout, periphery positioning, power grid design, routing channels, and macro assembly.
• Carry out, debug, and complete DRC, LVS, ERC, antenna, and associated physical verification checks with tools such as Calibre, ICV, or similar workflows.
• Support EM, IR review, power integrity, density, fill, DFM, dummy insertion, layout-dependent effects, and other requirements for tapeout.
• Collaborate with circuit designers to convert schematics into layouts, ensuring matching, symmetry, shielding, parasitic targets, and reliability constraints are maintained.
• Collaborate with PnR and integration teams to resolve top-level DRC, LVS, pin access, boundary, routing, power-grid, and macro-integration issues.
• Implement and advance layout methodology, checklists, reusable practices, and quality standards for consistent memory IP delivery.
• Collaborate with foundry, CAD, and methodology teams on rule interpretation, deck behavior, waivers, and advanced-node process constraints.
• Review layouts, mentor junior engineers, and help raise layout quality and execution rigor across the team.

Key Required Skills

• Have a BSEE or equivalent experience
• 10+ years of custom IC layout experience, including 5+ years in SRAM, memory compiler, or full-custom memory IP layout.
• Hands-on participation in advanced CMOS technology initiatives, preferably concentrating on FinFET or GAA nodes at 5nm, 3nm, or smaller dimensions.
• Solid grasp of SRAM and memory layout principles.
• Extensive experience in Cadence Virtuoso applied to custom layout creation and assessment.
• Extensive experience in DRC, LVS debugging using Calibre, ICV, or similar physical verification tools.
• Experience with floorplanning, block-level routing, macro assembly, pin planning, boundary, interface management, and top-level physical verification.
• Direct familiarity with advanced-node layout limitations and layout-dependent phenomena, including LOD, density, fill, matching, symmetry, shielding, electromigration, IR drop, and DFM or similar expertise.
• Ability to work effectively with circuit build, physical build, integration, CAD, and foundry teams.
• Clear communication, strong ownership, good judgment, and the ability to mentor other engineers.
• Knowledge of layout automation or AI tools is a definite plus.