Memory Layout Design Engineer

Broadcom; Bengaluru; On-site; INR 1,200,000 - 2,400,000; Full time

Job summary

Broadcom in Bengaluru seeks a layout engineer with 3+ years of experience in memory and digital layout. Proficiency with Cadence tools (Virtuoso, Layout XL, Schematic Capture) and CALIBRE/Hercules is required, with strong knowledge of submicron processes (A14, 2nm-7nm). You will contribute to floor-planning, design rules, and end-to-end deliverables.

The role emphasizes collaboration with SOC/library teams, adaptability to new methodologies, and timely project execution to meet quality targets.

Qualifications

• Minimum 3 years of experience with strong layout knowledge.
• Bachelor's degree required.
• Proficiency in using Cadence tools (Virtuoso Layout, Layout XL, Cadence Schematic Capture, and verification tools - CALIBRE & Hercules).
• Strong layout knowledge in submicron processes (e.g., A14, 2nm, 3nm, 5nm, 7nm).
• Experience in digital layout (Standard cell, Memory, I/O); analog layout experience is a plus.

Responsibilities

• Understand and apply layout guidelines, new process rules, and technical requirements for good quality layout.
• Manage scheduling, timelines, and layout floor-planning.
• Responsible for start-to-end deliverables with quality within the planned schedule.
• Adapt quickly to new methodologies, remain open to new ideas, and communicate effectively with the SOC/library team.

Skills

Layout knowledge

Digital layout

Leadership

Layout automation

Scripting

Education

Bachelor's degree

Tools

Virtuoso Layout

Layout XL

Cadence Schematic Capture

CALIBRE

Hercules

Job description

• Minimum 3 years of experience with strong layout knowledge.
• Bachelor's degree required.
• Proficiency in using Cadence tools (Virtuoso Layout, Layout XL, Cadence Schematic Capture, and verification tools - CALIBRE & Hercules).
• Strong layout knowledge in submicron processes (e.g., A14, 2nm, 3nm, 5nm, 7nm).
• Experience in digital layout (Standard cell, Memory, I/O); analog layout experience is a plus.

Job Description:

Job Requirements:

• Minimum 3 years of experience with strong layout knowledge.
• Bachelor's degree required.
• Proficiency in using Cadence tools (Virtuoso Layout, Layout XL, Cadence Schematic Capture, and verification tools - CALIBRE & Hercules).
• Strong layout knowledge in submicron processes (e.g., A14, 2nm, 3nm, 5nm, 7nm).
• Experience in digital layout (Standard cell, Memory, I/O); analog layout experience is a plus.

Job Description:

• Understand and apply layout guidelines, new process rules, and technical requirements for good quality layout.
• Manage scheduling, timelines, and layout floor-planning.
• Responsible for start-to-end deliverables with quality within the planned schedule.
• Adapt quickly to new methodologies, remain open to new ideas, and communicate effectively with the SOC/library team.

Skill Set (Memory):

• Strong experience in Memory layout design and physical verification (LVS, DRC, ERC, Antenna, ElectroMigration) in CMOS processes.
• Experience with Cadence Layout tools (VIRTUOSO XL, VXL, or EXL) and CALIBRE verification tools.
• Proficiency in floor-planning, hierarchy layout, and chip integration.
• Understanding of memory architecture, RC requirements, and the ability to plan signal and power based on layout guidelines.
• Knowledge of AI, automation in layout, Script Programming, and SKILL Programming is a plus.
• Ability to lead, train junior engineers, and manage projects effectively.
• Good knowledge of memory layout topology; experience with memory compilers is a plus.
• Ability to lead new technology reviews to document layout methodologies, flows, and guidelines.
• Self-reliant with the ability to work both independently and collaboratively.

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